| Line 41... |
Line 41... |
#include "execute.h"
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#include "execute.h"
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#include "except.h"
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#include "except.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "sched.h"
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#include "sched.h"
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#include "debug.h"
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DEFAULT_DEBUG_CHANNEL (pic);
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/* FIXME: This ugly hack will be removed once the bus architecture gets written
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/* FIXME: This ugly hack will be removed once the bus architecture gets written
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*/
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*/
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struct pic pic_state_int = { 1, 1 };
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struct pic pic_state_int = { 1, 1 };
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| Line 67... |
Line 65... |
static void
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static void
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pic_rep_int (void *dat)
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pic_rep_int (void *dat)
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{
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{
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if (cpu_state.sprs[SPR_PICSR])
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if (cpu_state.sprs[SPR_PICSR])
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{
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{
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TRACE ("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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}
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}
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}
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}
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/* Called whenever interrupts get enabled */
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/* Called whenever interrupts get enabled */
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| Line 92... |
Line 89... |
uint32_t lmask = 1 << line;
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uint32_t lmask = 1 << line;
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/* Disable doze and sleep mode */
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/* Disable doze and sleep mode */
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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cpu_state.sprs[SPR_PMR] &= ~(SPR_PMR_DME | SPR_PMR_SME);
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TRACE ("Asserting interrupt %d (%s).\n", line,
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(cpu_state.sprs[SPR_PICMR] & lmask) ? "Unmasked" : "Masked");
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/* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
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/* If PIC is disabled, don't set any register, just raise EXCEPT_INT */
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if (!config.pic.enabled)
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if (!config.pic.enabled)
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{
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{
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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if (cpu_state.sprs[SPR_SR] & SPR_SR_IEE)
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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except_handle (EXCEPT_INT, cpu_state.sprs[SPR_EEAR_BASE]);
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| Line 106... |
Line 100... |
}
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}
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if (cpu_state.pic_lines & lmask)
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if (cpu_state.pic_lines & lmask)
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{
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{
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/* No edge occured, warn about performance penalty and exit */
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/* No edge occured, warn about performance penalty and exit */
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WARN ("Int line %d did not change state\n", line);
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fprintf (stderr, "Warning: Int line %d did not change state\n", line);
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return;
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return;
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}
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}
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cpu_state.pic_lines |= lmask;
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cpu_state.pic_lines |= lmask;
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cpu_state.sprs[SPR_PICSR] |= lmask;
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cpu_state.sprs[SPR_PICSR] |= lmask;
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| Line 122... |
Line 116... |
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/* Clears an int on a pic line */
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/* Clears an int on a pic line */
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void
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void
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clear_interrupt (int line)
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clear_interrupt (int line)
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{
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{
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TRACE ("Clearing interrupt %d\n", line);
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cpu_state.pic_lines &= ~(1 << line);
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cpu_state.pic_lines &= ~(1 << line);
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if (!config.pic.edge_trigger)
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if (!config.pic.edge_trigger)
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cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
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cpu_state.sprs[SPR_PICSR] &= ~(1 << line);
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}
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}
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