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[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [support/] [dumpverilog.c] - Diff between revs 1748 and 1751

Rev 1748	Rev 1751
Line 51...	Line 51...
`"// Data out is not registered. Address bits specify dw-word (narrowest \n"\`	`"// Data out is not registered. Address bits specify dw-word (narrowest \n"\`
`"// addressed data is not byte but dw-word !). \n"\`	`"// addressed data is not byte but dw-word !). \n"\`
`"// There are still some bugs in generated output (dump word aligned regions)\n\n"\`	`"// There are still some bugs in generated output (dump word aligned regions)\n\n"\`
`"module %s(clk, data, addr, ce, we, disout);\n\n"\`	`"module %s(clk, data, addr, ce, we, disout);\n\n"\`
`"parameter dw = 32;\n"\`	`"parameter dw = 32;\n"\`
`"parameter amin = %d;\n\n"\`	`"parameter amin = %" PRIdREG ";\n\n"\`
`"parameter amax = %d;\n\n"\`	`"parameter amax = %" PRIdREG ";\n\n"\`
`"input clk;\n"\`	`"input clk;\n"\`
`"inout [dw-1:0] data;\n"\`	`"inout [dw-1:0] data;\n"\`
`"input [31:0] addr;\n"\`	`"input [31:0] addr;\n"\`
`"input ce;\n"\`	`"input ce;\n"\`
`"input we;\n"\`	`"input we;\n"\`