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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.10 2001/11/12 01:45:40 lampret
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// Revision 1.10 2001/11/12 01:45:40 lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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Line 104... |
// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [width-1:0] result;
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reg [width-1:0] result;
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reg [width-1:0] shifted_rotated;
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reg [width-1:0] shifted_rotated;
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reg flagforw;
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reg flagforw;
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reg flagcomp;
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reg flag_we;
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reg flag_we;
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integer d1;
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integer d1;
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integer d2;
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integer d2;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_a;
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wire [width-1:0] comp_b;
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wire [width-1:0] comp_b;
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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wire a_eq_b;
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wire a_eq_b;
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wire a_lt_b;
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wire a_lt_b;
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`endif
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`endif
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wire [width-1:0] result_sum;
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wire [width-1:0] result_and;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`endif
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assign result_sum = a + b;
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assign result_and = a & b;
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//
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//
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// Simulation check for bad ALU behavior
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// Simulation check for bad ALU behavior
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//
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//
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`ifdef OR1200_WARNINGS
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`ifdef OR1200_WARNINGS
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Line 144... |
`endif
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`endif
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//
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//
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// Central part of the ALU
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// Central part of the ALU
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//
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//
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always @(alu_op or a or b or macrc_op or shifted_rotated or mult_mac_result) begin
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always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
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casex (alu_op) // synopsys parallel_case full_case
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casex (alu_op) // synopsys parallel_case full_case
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`OR1200_ALUOP_SHROT : begin
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`OR1200_ALUOP_SHROT : begin
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result = shifted_rotated;
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result = shifted_rotated;
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flag_we = 1'b0;
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end
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end
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`OR1200_ALUOP_ADD : begin
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`OR1200_ALUOP_ADD : begin
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result = a + b;
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result = result_sum;
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flag_we = 1'b0;
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end
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end
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`OR1200_ALUOP_SUB : begin
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`OR1200_ALUOP_SUB : begin
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result = a - b;
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result = a - b;
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flag_we = 1'b0;
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end
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end
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`OR1200_ALUOP_XOR : begin
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`OR1200_ALUOP_XOR : begin
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result = a ^ b;
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result = a ^ b;
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flag_we = 1'b0;
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end
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end
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`OR1200_ALUOP_OR : begin
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`OR1200_ALUOP_OR : begin
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result = a | b;
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result = a | b;
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flag_we = 1'b0;
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end
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end
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`OR1200_ALUOP_IMM : begin
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`OR1200_ALUOP_IMM : begin
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result = b;
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result = b;
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flag_we = 1'b0;
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end
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end
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`OR1200_ALUOP_MOVHI : begin
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`OR1200_ALUOP_MOVHI : begin
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if (macrc_op) begin
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if (macrc_op) begin
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result = mult_mac_result;
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result = mult_mac_result;
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flag_we = 1'b0;
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end
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end
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else begin
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else begin
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result = b << 16;
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result = b << 16;
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flag_we = 1'b0;
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end
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end
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end
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end
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`OR1200_ALUOP_MUL : begin
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`OR1200_ALUOP_MUL : begin
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result = mult_mac_result;
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result = mult_mac_result;
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`ifdef OR1200_VERBOSE
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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// synopsys translate_off
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$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
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$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
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// synopsys translate_on
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// synopsys translate_on
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`endif
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`endif
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flag_we = 1'b0;
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end
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end
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// synopsys translate_off
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// synopsys translate_off
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`ifdef OR1200_SIM_ALU_DIV
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`ifdef OR1200_SIM_ALU_DIV
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`OR1200_ALUOP_DIV : begin
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`OR1200_ALUOP_DIV : begin
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d1 = a;
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d1 = a;
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Line 190... |
$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
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$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
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if (d2)
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if (d2)
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result = d1 / d2;
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result = d1 / d2;
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else
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else
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result = 32'h00000000;
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result = 32'h00000000;
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flag_we = 1'b0;
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end
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end
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`endif
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`endif
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`ifdef OR1200_SIM_ALU_DIVU
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`ifdef OR1200_SIM_ALU_DIVU
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`OR1200_ALUOP_DIVU : begin
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`OR1200_ALUOP_DIVU : begin
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if (b)
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if (b)
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result = a / b;
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result = a / b;
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else
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else
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result = 32'h00000000;
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result = 32'h00000000;
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flag_we = 1'b0;
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end
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end
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`endif
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`endif
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// synopsys translate_on
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// synopsys translate_on
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`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
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result = result_and;
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end
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endcase
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end
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//
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// Generate flag and flag write enable
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//
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always @(alu_op or result_sum or result_and or flagcomp) begin
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casex (alu_op) // synopsys parallel_case full_case
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`OR1200_ALUOP_ADD : begin
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flagforw = (result_sum == 32'h0000_0000);
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flag_we = 1'b0;
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end
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`OR1200_ALUOP_AND: begin
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flagforw = (result_and == 32'h0000_0000);
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flag_we = 1'b0;
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end
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`OR1200_ALUOP_COMP: begin
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`OR1200_ALUOP_COMP: begin
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flagforw = flagcomp;
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flag_we = 1'b1;
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flag_we = 1'b1;
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result = 32'd0;
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end
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end
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default : begin // `OR1200_ALUOP_AND
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default: begin
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result = a & b;
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flagforw = 1'b0;
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flag_we = 1'b0;
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flag_we = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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Line 257... |
//
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//
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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always @(comp_op or a_eq_b or a_lt_b) begin
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always @(comp_op or a_eq_b or a_lt_b) begin
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case(comp_op[2:0]) // synopsys parallel_case full_case
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case(comp_op[2:0]) // synopsys parallel_case full_case
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`OR1200_COP_SFEQ:
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`OR1200_COP_SFEQ:
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flagforw = a_eq_b;
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flagcomp = a_eq_b;
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`OR1200_COP_SFNE:
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`OR1200_COP_SFNE:
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flagforw = ~a_eq_b;
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flagcomp = ~a_eq_b;
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`OR1200_COP_SFGT:
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`OR1200_COP_SFGT:
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flagforw = ~(a_eq_b | a_lt_b);
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flagcomp = ~(a_eq_b | a_lt_b);
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`OR1200_COP_SFGE:
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`OR1200_COP_SFGE:
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flagforw = ~a_lt_b;
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flagcomp = ~a_lt_b;
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`OR1200_COP_SFLT:
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`OR1200_COP_SFLT:
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flagforw = a_lt_b;
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flagcomp = a_lt_b;
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`OR1200_COP_SFLE:
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`OR1200_COP_SFLE:
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flagforw = a_eq_b | a_lt_b;
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flagcomp = a_eq_b | a_lt_b;
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// synopsys translate_off
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default:
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default:
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flagforw = 1'bx;
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flagcomp = 1'b0;
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// synopsys translate_on
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endcase
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endcase
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end
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end
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`endif
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`endif
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//
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//
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| Line 267... |
Line 281... |
//
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//
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`ifdef OR1200_IMPL_ALU_COMP2
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`ifdef OR1200_IMPL_ALU_COMP2
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always @(comp_op or comp_a or comp_b) begin
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always @(comp_op or comp_a or comp_b) begin
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case(comp_op[2:0]) // synopsys parallel_case full_case
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case(comp_op[2:0]) // synopsys parallel_case full_case
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`OR1200_COP_SFEQ:
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`OR1200_COP_SFEQ:
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flagforw = (comp_a == comp_b);
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flagcomp = (comp_a == comp_b);
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`OR1200_COP_SFNE:
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`OR1200_COP_SFNE:
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flagforw = (comp_a != comp_b);
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flagcomp = (comp_a != comp_b);
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`OR1200_COP_SFGT:
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`OR1200_COP_SFGT:
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flagforw = (comp_a > comp_b);
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flagcomp = (comp_a > comp_b);
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`OR1200_COP_SFGE:
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`OR1200_COP_SFGE:
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flagforw = (comp_a >= comp_b);
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flagcomp = (comp_a >= comp_b);
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`OR1200_COP_SFLT:
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`OR1200_COP_SFLT:
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flagforw = (comp_a < comp_b);
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flagcomp = (comp_a < comp_b);
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`OR1200_COP_SFLE:
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`OR1200_COP_SFLE:
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flagforw = (comp_a <= comp_b);
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flagcomp = (comp_a <= comp_b);
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// synopsys translate_off
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default:
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default:
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flagforw = 1'bx;
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flagcomp = 1'b0;
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// synopsys translate_on
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endcase
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endcase
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end
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end
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`endif
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`endif
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endmodule
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endmodule
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