| Line 43... |
Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.7 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.6 2002/02/01 19:56:54 lampret
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// Revision 1.6 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.5 2002/01/28 01:15:59 lampret
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// Revision 1.5 2002/01/28 01:15:59 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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| Line 122... |
Line 125... |
// Clk & Rst
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// Clk & Rst
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clk, rst,
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clk, rst,
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// Insn interface
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// Insn interface
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ic_en,
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ic_en,
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icpu_adr_o, icpu_cycstb_o, icpu_we_o, icpu_sel_o, icpu_tag_o,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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immu_en,
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immu_en,
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// Debug unit
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// Debug unit
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ex_insn, ex_freeze, branch_op,
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ex_insn, ex_freeze, branch_op,
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| Line 163... |
Line 166... |
// Insn (IC) interface
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// Insn (IC) interface
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//
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//
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output ic_en;
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output ic_en;
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output [31:0] icpu_adr_o;
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output [31:0] icpu_adr_o;
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output icpu_cycstb_o;
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output icpu_cycstb_o;
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output icpu_we_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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input [31:0] icpu_dat_i;
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input [31:0] icpu_dat_i;
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input icpu_ack_i;
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input icpu_ack_i;
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input icpu_rty_i;
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input icpu_rty_i;
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| Line 325... |
Line 327... |
wire except_ibuserr;
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wire except_ibuserr;
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wire except_dbuserr;
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wire except_dbuserr;
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wire abort_ex;
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wire abort_ex;
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//
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//
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// icpu_we_o
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//
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assign icpu_we_o = 1'b0;
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//
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// Send exceptions to Debug Unit
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// Send exceptions to Debug Unit
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//
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//
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assign du_except = except_stop;
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assign du_except = except_stop;
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//
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//
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| Line 369... |
Line 366... |
.rst(rst),
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.rst(rst),
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.icpu_adr_o(icpu_adr_o),
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.icpu_adr_o(icpu_adr_o),
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.icpu_cycstb_o(icpu_cycstb_o),
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.icpu_cycstb_o(icpu_cycstb_o),
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.icpu_sel_o(icpu_sel_o),
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.icpu_sel_o(icpu_sel_o),
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.icpu_tag_o(icpu_tag_o),
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.icpu_tag_o(icpu_tag_o),
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.icpu_ack_i(icpu_ack_i),
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.icpu_rty_i(icpu_rty_i),
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.icpu_rty_i(icpu_rty_i),
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.icpu_err_i(icpu_err_i),
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.icpu_adr_i(icpu_adr_i),
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.icpu_adr_i(icpu_adr_i),
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.branch_op(branch_op),
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.branch_op(branch_op),
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.except_type(except_type),
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.except_type(except_type),
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.except_start(except_start),
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.except_start(except_start),
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| Line 388... |
Line 383... |
.epcr(epcr),
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.epcr(epcr),
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.spr_dat_i(spr_dat_cpu),
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.spr_dat_i(spr_dat_cpu),
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.spr_pc_we(pc_we),
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.spr_pc_we(pc_we),
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.genpc_refetch(genpc_refetch),
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.genpc_refetch(genpc_refetch),
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.genpc_freeze(genpc_freeze),
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.genpc_freeze(genpc_freeze),
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.flushpipe(flushpipe),
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.no_more_dslot(no_more_dslot)
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.no_more_dslot(no_more_dslot)
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);
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);
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//
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//
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// Instantiation of instruction fetch block
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// Instantiation of instruction fetch block
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| Line 592... |
Line 586... |
.esr_we(esr_we),
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.esr_we(esr_we),
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.pc_we(pc_we),
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.pc_we(pc_we),
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.epcr(epcr),
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.epcr(epcr),
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.eear(eear),
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.eear(eear),
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.esr(esr),
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.esr(esr),
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.except_start(except_start),
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.except_started(except_started),
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.except_started(except_started),
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.sr(sr),
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.sr(sr),
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.branch_op(branch_op)
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.branch_op(branch_op)
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);
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);
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//
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//
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// Instantiation of load/store unit
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// Instantiation of load/store unit
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//
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//
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or1200_lsu or1200_lsu(
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or1200_lsu or1200_lsu(
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.clk(clk),
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.rst(rst),
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.addrbase(operand_a),
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.addrbase(operand_a),
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.addrofs(lsu_addrofs),
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.addrofs(lsu_addrofs),
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.lsu_op(lsu_op),
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.lsu_op(lsu_op),
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.lsu_datain(operand_b),
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.lsu_datain(operand_b),
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.lsu_dataout(lsu_dataout),
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.lsu_dataout(lsu_dataout),
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.lsu_stall(lsu_stall),
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.lsu_stall(lsu_stall),
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.lsu_unstall(lsu_unstall),
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.lsu_unstall(lsu_unstall),
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.du_stall(du_stall),
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.du_stall(du_stall),
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.flushpipe(flushpipe),
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.except_align(except_align),
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.except_align(except_align),
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.except_dtlbmiss(except_dtlbmiss),
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.except_dtlbmiss(except_dtlbmiss),
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.except_dmmufault(except_dmmufault),
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.except_dmmufault(except_dmmufault),
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.except_dbuserr(except_dbuserr),
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.except_dbuserr(except_dbuserr),
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| Line 727... |
Line 717... |
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//
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//
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// Instantiation of configuration registers
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// Instantiation of configuration registers
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//
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//
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or1200_cfgr or1200_cfgr(
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or1200_cfgr or1200_cfgr(
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.clk(clk),
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.rst(clk),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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.spr_dat_o(spr_dat_cfgr)
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.spr_dat_o(spr_dat_cfgr)
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);
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);
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endmodule
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endmodule
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