URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 512 and 536

Rev 512	Rev 536
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/01/03 21:23:03 lampret`
	`// Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.20 2001/12/04 05:02:36 lampret`	`// Revision 1.20 2001/12/04 05:02:36 lampret`
`// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32`	`// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32`
Line 155...	Line 158...
`//`	`//`
`// Register OR1200 WISHBONE outputs`	`// Register OR1200 WISHBONE outputs`
`// (at the moment correct operation`	`// (at the moment correct operation`
`// only with registered outputs)`	`// only with registered outputs)`
`//`	`//`
//`define OR1200_REGISTERED_OUTPUTS	`define OR1200_REGISTERED_OUTPUTS

`//`	`//`
`// Register OR1200 WISHBNE inputs`	`// Register OR1200 WISHBNE inputs`
`//`	`//`
`define OR1200_REGISTERED_INPUTS	`define OR1200_REGISTERED_INPUTS