URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_du.v] - Diff between revs 504 and 562

Rev 504	Rev 562
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/01/03 08:16:15 lampret`
	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
	`//`
`// Revision 1.12 2001/11/30 18:58:00 simons`	`// Revision 1.12 2001/11/30 18:58:00 simons`
`// Trap insn couses break after exits ex_insn.`	`// Trap insn couses break after exits ex_insn.`
`//`	`//`
`// Revision 1.11 2001/11/23 08:38:51 lampret`	`// Revision 1.11 2001/11/23 08:38:51 lampret`
`// Changed DSR/DRR behavior and exception detection.`	`// Changed DSR/DRR behavior and exception detection.`
Line 283...	Line 286...
// DAMJAN \| ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]	// DAMJAN \| ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
\| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]	\| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif	`endif
`;`	`;`
`else`	`else`
`dbg_bp_r <= #1 1'b0;`	`dbg_bp_r <= #1 \|except_stop;`

`//`	`//`
`// Write to DMR1`	`// Write to DMR1`
`//`	`//`
`ifdef OR1200_DU_DMR1	`ifdef OR1200_DU_DMR1