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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// Revision 1.3 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// Clock and reset
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// Clock and reset
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clk, rst,
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clk, rst,
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// External i/f to IC
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// External i/f to IC
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
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icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
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icpu_rty_i, icpu_adr_i,
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// Internal i/f
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// Internal i/f
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branch_op, except_type, except_prefix,
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branch_op, except_type, except_prefix,
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branch_addrofs, lr_restor, flag, taken, except_start,
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branch_addrofs, lr_restor, flag, taken, except_start,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
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genpc_freeze, flushpipe, no_more_dslot
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genpc_freeze, no_more_dslot
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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//
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//
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output [31:0] icpu_adr_o;
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output [31:0] icpu_adr_o;
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output icpu_cycstb_o;
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output icpu_cycstb_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_sel_o;
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output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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input icpu_ack_i;
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input icpu_rty_i;
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input icpu_rty_i;
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input icpu_err_i;
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input [31:0] icpu_adr_i;
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input [31:0] icpu_adr_i;
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//
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//
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// Internal i/f
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// Internal i/f
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//
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//
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input [31:0] epcr;
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input [31:0] epcr;
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input [31:0] spr_dat_i;
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input [31:0] spr_dat_i;
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input spr_pc_we;
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input spr_pc_we;
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input genpc_refetch;
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input genpc_refetch;
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input genpc_freeze;
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input genpc_freeze;
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input flushpipe;
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input no_more_dslot;
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input no_more_dslot;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [31:2] pcreg;
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reg [31:2] pcreg;
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reg [31:0] pc;
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reg [31:0] pc;
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reg taken; /* Set to in case of jump or taken branch */
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reg taken; /* Set to in case of jump or taken branch */
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reg dslot; /* set when fetching delay slot insn */
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reg btarget; /* set when fetching branch target insns */
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//
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//
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// Address of insn to be fecthed
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// Address of insn to be fecthed
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//
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//
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
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