| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.6 2001/10/21 17:57:16 lampret
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// Revision 1.6 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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| Line 80... |
Line 83... |
// Rst and clk
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// Rst and clk
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clk, rst,
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clk, rst,
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// CPU i/f
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// CPU i/f
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ic_en, immu_en, supv, icpu_adr_i, icpu_cyc_i, icpu_stb_i,
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ic_en, immu_en, supv, icpu_adr_i, icpu_cyc_i, icpu_stb_i,
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icpu_adr_o, icpu_tag_o, icpu_err_o,
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icpu_adr_o, icpu_tag_o, icpu_rty_o, icpu_err_o,
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// SPR access
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// SPR access
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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// IC i/f
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// IC i/f
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icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cyc_o, icimmu_stb_o, icimmu_ci_o
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icimmu_rty_i, icimmu_err_i, icimmu_tag_i, icimmu_adr_o, icimmu_cyc_o, icimmu_stb_o, icimmu_ci_o
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);
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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| Line 113... |
Line 116... |
input [aw-1:0] icpu_adr_i;
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input [aw-1:0] icpu_adr_i;
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input icpu_cyc_i;
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input icpu_cyc_i;
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input icpu_stb_i;
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input icpu_stb_i;
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output [aw-1:0] icpu_adr_o;
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output [aw-1:0] icpu_adr_o;
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output [3:0] icpu_tag_o;
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output [3:0] icpu_tag_o;
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output icpu_rty_o;
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output icpu_err_o;
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output icpu_err_o;
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//
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//
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// SPR access
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// SPR access
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//
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//
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| Line 127... |
Line 131... |
output [31:0] spr_dat_o;
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output [31:0] spr_dat_o;
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//
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//
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// IC I/F
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// IC I/F
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//
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//
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input icimmu_rty_i;
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input icimmu_err_i;
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input icimmu_err_i;
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input [3:0] icimmu_tag_i;
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input [3:0] icimmu_tag_i;
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output [aw-1:0] icimmu_adr_o;
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output [aw-1:0] icimmu_adr_o;
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output icimmu_cyc_o;
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output icimmu_cyc_o;
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output icimmu_stb_o;
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output icimmu_stb_o;
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| Line 148... |
Line 153... |
wire itlb_en;
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wire itlb_en;
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wire itlb_ci;
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wire itlb_ci;
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wire itlb_done;
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wire itlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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reg icpu_cyc_dlyd;
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reg icpu_stb_dlyd;
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reg [31:0] icpu_adr_o;
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reg [31:0] icpu_adr_o;
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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| Line 188... |
Line 191... |
assign spr_dat_o = 32'h00000000;
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assign spr_dat_o = 32'h00000000;
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assign icimmu_adr_o = icpu_adr_i;
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assign icimmu_adr_o = icpu_adr_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icpu_tag_o = icimmu_tag_i;
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assign icimmu_cyc_o = icpu_cyc_i;
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assign icimmu_cyc_o = icpu_cyc_i;
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assign icimmu_stb_o = icpu_stb_i;
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assign icimmu_stb_o = icpu_stb_i;
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assign icpu_rty_o = icimmu_rty_i;
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assign icpu_err_o = icimmu_err_i;
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assign icpu_err_o = icimmu_err_i;
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assign icimmu_ci_o = !icpu_adr_i[30];
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assign icimmu_ci_o = icpu_adr_i[31];
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`else
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`else
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//
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//
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// ITLB SPR access
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// ITLB SPR access
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| Line 213... |
Line 217... |
// OR1200_DTAG_PE - Page fault Exception
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// OR1200_DTAG_PE - Page fault Exception
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//
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//
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assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : icimmu_tag_i;
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assign icpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : icimmu_tag_i;
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//
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//
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// icpu_rty_o
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//
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// assign icpu_rty_o = !icpu_err_o & icimmu_rty_i;
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assign icpu_rty_o = icimmu_rty_i;
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//
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// icpu_err_o
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// icpu_err_o
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//
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//
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assign icpu_err_o = miss | fault | icimmu_err_i;
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assign icpu_err_o = miss | fault | icimmu_err_i;
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//
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//
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// Delay WISHBONE control signals in case IC is disabled and IMMU is
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// Assert itlb_done one clock cycle after new address is first presented and tlb is enabled.
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// enabled to prevent premature external BIU access.
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//
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//
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always @(posedge rst or posedge clk)
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assign itlb_done = (icpu_adr_i == icpu_adr_o) & itlb_en;
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if (rst)
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icpu_cyc_dlyd <= #1 1'b0;
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else
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icpu_cyc_dlyd <= #1 ~(miss | fault) & icpu_cyc_i;
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always @(posedge rst or posedge clk)
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if (rst)
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icpu_stb_dlyd <= #1 1'b0;
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else
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icpu_stb_dlyd <= #1 ~(miss | fault) & icpu_stb_i;
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//
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//
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// Cut transfer if something goes wrong with translation. If IC is disabled,
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// use delayed signals.
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// use delayed signals.
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//
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//
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assign icimmu_cyc_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_cyc_dlyd : (miss | fault) ? 1'b0 : icpu_cyc_i;
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assign icimmu_cyc_o = (!ic_en & immu_en) ? ~(miss | fault) & itlb_done & icpu_cyc_i : (miss | fault) ? 1'b0 : icpu_cyc_i;
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assign icimmu_stb_o = (!ic_en & immu_en) ? ~(miss | fault) & icpu_stb_dlyd : (miss | fault) ? 1'b0 : icpu_stb_i;
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assign icimmu_stb_o = (!ic_en & immu_en) ? ~(miss | fault) & itlb_done & icpu_stb_i : (miss | fault) ? 1'b0 : icpu_stb_i;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : 1'b0;
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assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : icpu_adr_i[31];
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when IMMU is disabled
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// simply equal when IMMU is disabled
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//
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//
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| Line 258... |
Line 258... |
assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;
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assign spr_dat_o = itlb_spr_access ? itlb_dat_o : 32'h00000000;
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//
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//
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// Page fault exception logic
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// Page fault exception logic
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//
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//
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assign fault = itlb_en & itlb_done &
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assign fault = itlb_done &
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( (!supv & !itlb_uxe) // Execute in user mode not enabled
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( (!supv & !itlb_uxe) // Execute in user mode not enabled
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|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
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|| (supv & !itlb_sxe)); // Execute in supv mode not enabled
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//
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//
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// TLB Miss exception logic
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// TLB Miss exception logic
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//
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//
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assign miss = itlb_en & itlb_done & !itlb_hit;
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assign miss = itlb_done & !itlb_hit;
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//
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//
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// ITLB Enable
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// ITLB Enable
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//
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//
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assign itlb_en = immu_en & icpu_cyc_i & icpu_stb_i;
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assign itlb_en = immu_en & icpu_cyc_i & icpu_stb_i;
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| Line 288... |
Line 288... |
.hit(itlb_hit),
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.hit(itlb_hit),
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.ppn(itlb_ppn),
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.ppn(itlb_ppn),
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.uxe(itlb_uxe),
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.uxe(itlb_uxe),
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.sxe(itlb_sxe),
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.sxe(itlb_sxe),
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.ci(itlb_ci),
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.ci(itlb_ci),
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.done(itlb_done),
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// SPR access
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// SPR access
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.spr_cs(itlb_spr_access),
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.spr_cs(itlb_spr_access),
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.spr_write(spr_write),
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.spr_write(spr_write),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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