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[/] [or1k/] [tags/] [rel_10/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Diff between revs 775 and 788

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Rev 775 Rev 788
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.6  2002/03/28 19:10:40  lampret
 
// Optimized cache controller FSM.
 
//
// Revision 1.1.1.1  2002/03/21 16:55:45  lampret
// Revision 1.1.1.1  2002/03/21 16:55:45  lampret
// First import of the "new" XESS XSV environment.
// First import of the "new" XESS XSV environment.
//
//
//
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Revision 1.5  2002/02/11 04:33:17  lampret
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`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_CLOAD      3'd1
`define OR1200_DCFSM_CLOAD      3'd1
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_CSTORE     3'd3
`define OR1200_DCFSM_CSTORE     3'd3
`define OR1200_DCFSM_SREFILL4   3'd4
`define OR1200_DCFSM_SREFILL4   3'd4
`define OR1200_DCFSM_ILOAD      3'd5
 
`define OR1200_DCFSM_ISTORE     3'd6
 
 
 
//
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
//
 
 

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