| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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| Line 93... |
Line 96... |
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//
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//
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// Mux to memdata[31:24]
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// Mux to memdata[31:24]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
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{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
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{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
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{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
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default : memdata_hh = regdata[31:24];
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default : memdata_hh = regdata[31:24];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[23:16]
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// Mux to memdata[23:16]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
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{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
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default : memdata_hl = regdata[7:0];
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default : memdata_hl = regdata[7:0];
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endcase
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endcase
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end
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end
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//
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//
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// Mux to memdata[15:8]
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// Mux to memdata[15:8]
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//
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//
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always @(lsu_op or addr or regdata) begin
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always @(lsu_op or addr or regdata) begin
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casex({lsu_op, addr[1:0]}) // synopsys full_case parallel_case
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casex({lsu_op, addr[1:0]}) // synopsys parallel_case
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{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
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{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
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default : memdata_lh = regdata[15:8];
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default : memdata_lh = regdata[15:8];
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endcase
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endcase
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end
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end
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