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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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// Revision 1.3 2002/01/19 09:27:49 lampret
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// Revision 1.3 2002/01/19 09:27:49 lampret
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// SR[TEE] should be zero after reset.
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// SR[TEE] should be zero after reset.
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//
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//
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// Revision 1.2 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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Line 101... |
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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// From/to other RISC units
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// From/to other RISC units
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_dat_dmmu, spr_dat_immu, spr_dat_du,
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spr_addr, spr_dataout, spr_cs, spr_we,
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spr_addr, spr_dat_o, spr_cs, spr_we,
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du_addr, du_dat_du, du_read,
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du_addr, du_dat_du, du_read,
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du_write
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du_write, du_dat_cpu
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);
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);
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parameter width = `OR1200_OPERAND_WIDTH;
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parameter width = `OR1200_OPERAND_WIDTH;
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Line 154... |
input [31:0] spr_dat_pm; // Data from PM
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input [31:0] spr_dat_pm; // Data from PM
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input [31:0] spr_dat_dmmu; // Data from DMMU
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input [31:0] spr_dat_dmmu; // Data from DMMU
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input [31:0] spr_dat_immu; // Data from IMMU
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input [31:0] spr_dat_immu; // Data from IMMU
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input [31:0] spr_dat_du; // Data from DU
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input [31:0] spr_dat_du; // Data from DU
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output [31:0] spr_addr; // SPR Address
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output [31:0] spr_addr; // SPR Address
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output [31:0] spr_dataout; // Data to unit
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output [31:0] spr_dat_o; // Data to unit
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output [31:0] spr_cs; // Unit select
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output [31:0] spr_cs; // Unit select
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output spr_we; // SPR write enable
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output spr_we; // SPR write enable
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//
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//
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// To/from Debug Unit
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// To/from Debug Unit
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//
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//
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input [width-1:0] du_addr; // Address
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input [width-1:0] du_addr; // Address
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input [width-1:0] du_dat_du; // Data from DU to SPRS
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input [width-1:0] du_dat_du; // Data from DU to SPRS
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input du_read; // Read qualifier
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input du_read; // Read qualifier
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input du_write; // Write qualifier
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input du_write; // Write qualifier
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output [width-1:0] du_dat_cpu; // Data from SPRS to DU
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//
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//
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// Internal regs & wires
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// Internal regs & wires
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//
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//
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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reg [`OR1200_SR_WIDTH-1:0] sr; // SR
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Line 206... |
// OR from debug unit address
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// OR from debug unit address
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//
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//
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assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};
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assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};
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//
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//
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// SPR is written with dat_i from l.mtspr
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// SPR is written by debug unit or by l.mtspr
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// OR by debug unit
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//
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assign spr_dat_o = du_write ? du_dat_du : dat_i;
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//
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// debug unit data input:
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// - write into debug unit SPRs by debug unit itself
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// - read of SPRS by debug unit
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// - write into debug unit SPRs by l.mtspr
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//
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//
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assign spr_dataout = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
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assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
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//
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//
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// Write into SPRs when l.mtspr
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// Write into SPRs when l.mtspr
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//
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//
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assign spr_we = du_write | write_spr;
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assign spr_we = du_write | write_spr;
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Line 274... |
//
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//
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//
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//
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// What to write into SR
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// What to write into SR
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//
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//
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assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dataout[`OR1200_SR_WIDTH-2:0]};
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assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]};
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//
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//
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// Selects for system SPRs
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// Selects for system SPRs
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//
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//
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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Line 335... |
sr[`OR1200_SR_F] <= #1 flagforw;
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sr[`OR1200_SR_F] <= #1 flagforw;
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//
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//
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// MTSPR/MFSPR interface
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// MTSPR/MFSPR interface
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//
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//
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always @(sprs_op or spr_addr or spr_dataout or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
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spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
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case (sprs_op) // synopsys full_case parallel_case
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case (sprs_op) // synopsys full_case parallel_case
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`OR1200_ALUOP_MTSR : begin
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`OR1200_ALUOP_MTSR : begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: SPRS: mtspr (%h) <- %h", $time, spr_addr, spr_dataout);
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// synopsys translate_on
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`endif
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write_spr = 1'b1;
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write_spr = 1'b1;
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read_spr = 1'b0;
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read_spr = 1'b0;
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to_wbmux = 32'b0;
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to_wbmux = 32'b0;
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end
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end
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`OR1200_ALUOP_MFSR : begin
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`OR1200_ALUOP_MFSR : begin
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