| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/08/18 19:54:22 lampret
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// Added store buffer.
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//
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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//
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//
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Revision 1.6 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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| Line 116... |
Line 119... |
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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`ifdef OR1200_BIST
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// RAM BIST
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scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,
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`endif
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// Power Management
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// Power Management
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pm_cpustall_i,
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pm_cpustall_i,
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pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
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pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
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pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
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pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
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| Line 187... |
Line 194... |
output [1:0] dbg_is_o; // External Insn Fetch Status
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output [1:0] dbg_is_o; // External Insn Fetch Status
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output [10:0] dbg_wp_o; // Watchpoints Outputs
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output dbg_bp_o; // Breakpoint Output
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output dbg_bp_o; // Breakpoint Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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output [dw-1:0] dbg_dat_o; // External Data Output
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input scanb_rst,
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scanb_si,
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scanb_en,
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scanb_clk;
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output scanb_so;
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`endif
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//
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//
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// Power Management
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// Power Management
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//
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//
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input pm_cpustall_i;
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input pm_cpustall_i;
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output [3:0] pm_clksd_o;
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output [3:0] pm_clksd_o;
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| Line 355... |
Line 373... |
wire [31:0] ex_insn;
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wire [31:0] ex_insn;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
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wire [31:0] spr_dat_npc;
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wire [31:0] spr_dat_npc;
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wire [31:0] rf_dataw;
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wire [31:0] rf_dataw;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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wire scanb_immu_so;
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wire scanb_ic_so;
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wire scanb_dmmu_so;
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wire scanb_dc_so;
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wire scanb_immu_si = scanb_si;
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wire scanb_ic_si = scanb_immu_so;
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wire scanb_dmmu_si = scanb_ic_so;
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wire scanb_dc_si = scanb_dmmu_so;
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assign scanb_so = scanb_dc_so;
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`endif
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//
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//
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// Instantiation of Instruction WISHBONE BIU
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// Instantiation of Instruction WISHBONE BIU
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//
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//
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or1200_wb_biu iwb_biu(
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or1200_wb_biu iwb_biu(
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| Line 438... |
Line 471... |
or1200_immu_top or1200_immu_top(
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or1200_immu_top or1200_immu_top(
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// Rst and clk
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// Rst and clk
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.clk(clk_i),
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.clk(clk_i),
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.rst(rst_i),
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.rst(rst_i),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_immu_si),
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.scanb_so(scanb_immu_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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// CPU i/f
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// CPU i/f
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.ic_en(ic_en),
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.ic_en(ic_en),
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.immu_en(immu_en),
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.immu_en(immu_en),
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.supv(supv),
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.supv(supv),
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.icpu_adr_i(icpu_adr_cpu),
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.icpu_adr_i(icpu_adr_cpu),
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| Line 472... |
Line 514... |
//
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//
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or1200_ic_top or1200_ic_top(
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or1200_ic_top or1200_ic_top(
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.clk(clk_i),
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.clk(clk_i),
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.rst(rst_i),
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.rst(rst_i),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_ic_si),
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.scanb_so(scanb_ic_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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// IC and CPU/IMMU
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// IC and CPU/IMMU
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.ic_en(ic_en),
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.ic_en(ic_en),
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.icimmu_adr_i(icimmu_adr_immu),
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.icimmu_adr_i(icimmu_adr_immu),
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.icimmu_cycstb_i(icimmu_cycstb_immu),
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.icimmu_cycstb_i(icimmu_cycstb_immu),
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.icimmu_ci_i(icimmu_ci_immu),
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.icimmu_ci_i(icimmu_ci_immu),
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| Line 585... |
Line 636... |
or1200_dmmu_top or1200_dmmu_top(
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or1200_dmmu_top or1200_dmmu_top(
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// Rst and clk
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// Rst and clk
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.clk(clk_i),
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.clk(clk_i),
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.rst(rst_i),
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.rst(rst_i),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_dmmu_si),
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.scanb_so(scanb_dmmu_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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// CPU i/f
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// CPU i/f
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dmmu_en(dmmu_en),
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.dmmu_en(dmmu_en),
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.supv(supv),
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.supv(supv),
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.dcpu_adr_i(dcpu_adr_cpu),
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.dcpu_adr_i(dcpu_adr_cpu),
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| Line 617... |
Line 677... |
//
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//
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or1200_dc_top or1200_dc_top(
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or1200_dc_top or1200_dc_top(
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.clk(clk_i),
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.clk(clk_i),
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.rst(rst_i),
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.rst(rst_i),
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_dc_si),
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.scanb_so(scanb_dc_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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// DC and CPU/DMMU
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// DC and CPU/DMMU
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.dc_en(dc_en),
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.dc_en(dc_en),
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.dcdmmu_adr_i(dcdmmu_adr_dmmu),
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.dcdmmu_adr_i(dcdmmu_adr_dmmu),
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.dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu),
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.dcdmmu_cycstb_i(dcdmmu_cycstb_dmmu),
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.dcdmmu_ci_i(dcdmmu_ci_dmmu),
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.dcdmmu_ci_i(dcdmmu_ci_dmmu),
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