| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/10/17 20:04:41 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.8 2002/08/18 19:54:22 lampret
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// Revision 1.8 2002/08/18 19:54:22 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Revision 1.7 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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| Line 109... |
Line 112... |
// System
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// System
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clk_i, rst_i, pic_ints_i, clmode_i,
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clk_i, rst_i, pic_ints_i, clmode_i,
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// Instruction WISHBONE INTERFACE
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// Instruction WISHBONE INTERFACE
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iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
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iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
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iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_cab_o, iwb_dat_o,
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iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
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`ifdef OR1200_WB_CAB
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iwb_cab_o,
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`endif
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`ifdef OR1200_WB_B3
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iwb_cti_o, iwb_bte_o,
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`endif
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// Data WISHBONE INTERFACE
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// Data WISHBONE INTERFACE
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dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
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dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_cab_o, dwb_dat_o,
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dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
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`ifdef OR1200_WB_CAB
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dwb_cab_o,
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`endif
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`ifdef OR1200_WB_B3
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dwb_cti_o, dwb_bte_o,
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`endif
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,
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| Line 160... |
Line 174... |
output iwb_cyc_o; // cycle valid output
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output iwb_cyc_o; // cycle valid output
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output [aw-1:0] iwb_adr_o; // address bus outputs
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output [aw-1:0] iwb_adr_o; // address bus outputs
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output iwb_stb_o; // strobe output
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output iwb_stb_o; // strobe output
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output iwb_we_o; // indicates write transfer
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output iwb_we_o; // indicates write transfer
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output [3:0] iwb_sel_o; // byte select outputs
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output [3:0] iwb_sel_o; // byte select outputs
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output iwb_cab_o; // indicates consecutive address burst
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output [dw-1:0] iwb_dat_o; // output data bus
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output [dw-1:0] iwb_dat_o; // output data bus
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`ifdef OR1200_WB_CAB
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output iwb_cab_o; // indicates consecutive address burst
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`endif
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`ifdef OR1200_WB_B3
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output [2:0] iwb_cti_o; // cycle type identifier
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output [1:0] iwb_bte_o; // burst type extension
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`endif
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//
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//
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// Data WISHBONE interface
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// Data WISHBONE interface
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//
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//
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input dwb_clk_i; // clock input
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input dwb_clk_i; // clock input
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| Line 177... |
Line 197... |
output dwb_cyc_o; // cycle valid output
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output dwb_cyc_o; // cycle valid output
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output [aw-1:0] dwb_adr_o; // address bus outputs
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output [aw-1:0] dwb_adr_o; // address bus outputs
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output dwb_stb_o; // strobe output
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output dwb_stb_o; // strobe output
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output dwb_we_o; // indicates write transfer
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output dwb_we_o; // indicates write transfer
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output [3:0] dwb_sel_o; // byte select outputs
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output [3:0] dwb_sel_o; // byte select outputs
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output dwb_cab_o; // indicates consecutive address burst
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output [dw-1:0] dwb_dat_o; // output data bus
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output [dw-1:0] dwb_dat_o; // output data bus
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`ifdef OR1200_WB_CAB
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output dwb_cab_o; // indicates consecutive address burst
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`endif
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`ifdef OR1200_WB_B3
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output [2:0] dwb_cti_o; // cycle type identifier
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output [1:0] dwb_bte_o; // burst type extension
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`endif
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//
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//
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// External Debug Interface
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// External Debug Interface
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//
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//
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input dbg_stall_i; // External Stall Input
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input dbg_stall_i; // External Stall Input
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| Line 410... |
Line 436... |
.wb_cyc_o(iwb_cyc_o),
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.wb_cyc_o(iwb_cyc_o),
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.wb_adr_o(iwb_adr_o),
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.wb_adr_o(iwb_adr_o),
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.wb_stb_o(iwb_stb_o),
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.wb_stb_o(iwb_stb_o),
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.wb_we_o(iwb_we_o),
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.wb_we_o(iwb_we_o),
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.wb_sel_o(iwb_sel_o),
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.wb_sel_o(iwb_sel_o),
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.wb_cab_o(iwb_cab_o),
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.wb_dat_o(iwb_dat_o),
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.wb_dat_o(iwb_dat_o),
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`ifdef OR1200_WB_CAB
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.wb_cab_o(iwb_cab_o),
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`endif
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`ifdef OR1200_WB_B3
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.wb_cti_o(iwb_cti_o),
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.wb_bte_o(iwb_bte_o),
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`endif
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// Internal RISC bus
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// Internal RISC bus
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.biu_dat_i(icbiu_dat_ic),
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.biu_dat_i(icbiu_dat_ic),
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.biu_adr_i(icbiu_adr_ic),
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.biu_adr_i(icbiu_adr_ic),
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.biu_cyc_i(icbiu_cyc_ic),
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.biu_cyc_i(icbiu_cyc_ic),
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| Line 447... |
Line 479... |
.wb_cyc_o(dwb_cyc_o),
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.wb_cyc_o(dwb_cyc_o),
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.wb_adr_o(dwb_adr_o),
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.wb_adr_o(dwb_adr_o),
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.wb_stb_o(dwb_stb_o),
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.wb_stb_o(dwb_stb_o),
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.wb_we_o(dwb_we_o),
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.wb_we_o(dwb_we_o),
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.wb_sel_o(dwb_sel_o),
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.wb_sel_o(dwb_sel_o),
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.wb_cab_o(dwb_cab_o),
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.wb_dat_o(dwb_dat_o),
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.wb_dat_o(dwb_dat_o),
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`ifdef OR1200_WB_CAB
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.wb_cab_o(dwb_cab_o),
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`endif
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`ifdef OR1200_WB_B3
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.wb_cti_o(dwb_cti_o),
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.wb_bte_o(dwb_bte_o),
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`endif
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// Internal RISC bus
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// Internal RISC bus
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.biu_dat_i(sbbiu_dat_sb),
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.biu_dat_i(sbbiu_dat_sb),
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.biu_adr_i(sbbiu_adr_sb),
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.biu_adr_i(sbbiu_adr_sb),
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.biu_cyc_i(sbbiu_cyc_sb),
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.biu_cyc_i(sbbiu_cyc_sb),
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