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[/] [or1k/] [tags/] [rel_10/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Diff between revs 660 and 788

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Rev 660 Rev 788
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.5  2002/02/11 04:33:17  lampret
 
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
 
//
// Revision 1.4  2002/02/01 19:56:55  lampret
// Revision 1.4  2002/02/01 19:56:55  lampret
// Fixed combinational loops.
// Fixed combinational loops.
//
//
// Revision 1.3  2002/01/28 01:16:00  lampret
// Revision 1.3  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
Line 278... Line 281...
// CPU and insn memory subsystem
// CPU and insn memory subsystem
//
//
wire                    ic_en;
wire                    ic_en;
wire    [31:0]           icpu_adr_cpu;
wire    [31:0]           icpu_adr_cpu;
wire                    icpu_cycstb_cpu;
wire                    icpu_cycstb_cpu;
wire                    icpu_we_cpu;
 
wire    [3:0]            icpu_sel_cpu;
wire    [3:0]            icpu_sel_cpu;
wire    [3:0]            icpu_tag_cpu;
wire    [3:0]            icpu_tag_cpu;
wire    [31:0]           icpu_dat_ic;
wire    [31:0]           icpu_dat_ic;
wire                    icpu_ack_ic;
wire                    icpu_ack_ic;
wire    [31:0]           icpu_adr_immu;
wire    [31:0]           icpu_adr_immu;
Line 453... Line 455...
        // IC and CPU/IMMU
        // IC and CPU/IMMU
        .ic_en(ic_en),
        .ic_en(ic_en),
        .icimmu_adr_i(icimmu_adr_immu),
        .icimmu_adr_i(icimmu_adr_immu),
        .icimmu_cycstb_i(icimmu_cycstb_immu),
        .icimmu_cycstb_i(icimmu_cycstb_immu),
        .icimmu_ci_i(icimmu_ci_immu),
        .icimmu_ci_i(icimmu_ci_immu),
        .icpu_we_i(icpu_we_cpu),
 
        .icpu_sel_i(icpu_sel_cpu),
        .icpu_sel_i(icpu_sel_cpu),
        .icpu_tag_i(icpu_tag_cpu),
        .icpu_tag_i(icpu_tag_cpu),
        .icpu_dat_o(icpu_dat_ic),
        .icpu_dat_o(icpu_dat_ic),
        .icpu_ack_o(icpu_ack_ic),
        .icpu_ack_o(icpu_ack_ic),
        .icimmu_rty_o(icimmu_rty_ic),
        .icimmu_rty_o(icimmu_rty_ic),
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        // Connection IC and IFETCHER inside CPU
        // Connection IC and IFETCHER inside CPU
        .ic_en(ic_en),
        .ic_en(ic_en),
        .icpu_adr_o(icpu_adr_cpu),
        .icpu_adr_o(icpu_adr_cpu),
        .icpu_cycstb_o(icpu_cycstb_cpu),
        .icpu_cycstb_o(icpu_cycstb_cpu),
        .icpu_we_o(icpu_we_cpu),
 
        .icpu_sel_o(icpu_sel_cpu),
        .icpu_sel_o(icpu_sel_cpu),
        .icpu_tag_o(icpu_tag_cpu),
        .icpu_tag_o(icpu_tag_cpu),
        .icpu_dat_i(icpu_dat_ic),
        .icpu_dat_i(icpu_dat_ic),
        .icpu_ack_i(icpu_ack_ic),
        .icpu_ack_i(icpu_ack_ic),
        .icpu_rty_i(icpu_rty_immu),
        .icpu_rty_i(icpu_rty_immu),

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