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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/09/07 05:42:02 lampret
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// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
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//
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// Revision 1.7 2002/09/03 22:28:21 lampret
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// Revision 1.7 2002/09/03 22:28:21 lampret
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
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//
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//
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// Revision 1.6 2002/03/29 16:40:10 lampret
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// Revision 1.6 2002/03/29 16:40:10 lampret
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// Added a directive to ignore signed division variables that are only used in simulation.
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// Added a directive to ignore signed division variables that are only used in simulation.
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Line 144... |
wire a_lt_b;
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wire a_lt_b;
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`endif
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`endif
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wire [width-1:0] result_sum;
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wire [width-1:0] result_sum;
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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wire [width-1:0] result_csum;
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wire [width-1:0] result_csum;
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wire cy_csum;
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`endif
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`endif
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wire [width-1:0] result_and;
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wire [width-1:0] result_and;
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wire cyforw;
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wire cy_sum;
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reg cyforw;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
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`ifdef OR1200_IMPL_ALU_COMP1
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`ifdef OR1200_IMPL_ALU_COMP1
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assign a_eq_b = (comp_a == comp_b);
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assign a_eq_b = (comp_a == comp_b);
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assign a_lt_b = (comp_a < comp_b);
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assign a_lt_b = (comp_a < comp_b);
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`endif
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`endif
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assign {cyforw, result_sum} = a + b;
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assign {cy_sum, result_sum} = a + b;
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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assign {cyforw, result_csum} = a + b + carry;
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assign {cy_csum, result_csum} = a + b + carry;
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`endif
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`endif
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assign result_and = a & b;
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assign result_and = a & b;
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//
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//
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// Simulation check for bad ALU behavior
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// Simulation check for bad ALU behavior
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Line 291... |
end
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end
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//
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//
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// Generate SR[CY] write enable
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// Generate SR[CY] write enable
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//
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//
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always @(alu_op) begin
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always @(alu_op or cy_sum or cy_csum) begin
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casex (alu_op) // synopsys parallel_case
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casex (alu_op) // synopsys parallel_case
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`ifdef OR1200_IMPL_ADDC
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`ifdef OR1200_IMPL_ADDC
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`OR1200_ALUOP_ADD : begin
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cyforw = cy_sum;
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cy_we = 1'b1;
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end
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`OR1200_ALUOP_ADDC : begin
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`OR1200_ALUOP_ADDC : begin
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cyforw = cy_csum;
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cy_we = 1'b1;
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cy_we = 1'b1;
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end
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end
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`endif
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`endif
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default: begin
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default: begin
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cyforw = 1'b0;
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cy_we = 1'b0;
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cy_we = 1'b0;
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end
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end
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endcase
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endcase
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end
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end
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