URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_13/] [or1200/] [rtl/] [verilog/] [or1200_ctrl.v] - Diff between revs 504 and 562

Rev 504	Rev 562
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2002/01/03 08:16:15 lampret`
	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
	`//`
`// Revision 1.14 2001/11/30 18:59:17 simons`	`// Revision 1.14 2001/11/30 18:59:17 simons`
`// force_dslot_fetch does not work - allways zero.`	`// force_dslot_fetch does not work - allways zero.`
`//`	`//`
`// Revision 1.13 2001/11/20 18:46:15 simons`	`// Revision 1.13 2001/11/20 18:46:15 simons`
`// Break point bug fixed`	`// Break point bug fixed`
Line 428...	Line 431...
`// Instruction latch in wb_insn`	`// Instruction latch in wb_insn`
`//`	`//`
`always @(posedge clk or posedge rst) begin`	`always @(posedge clk or posedge rst) begin`
`if (rst)`	`if (rst)`
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F};	wb_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
	`else if (flushpipe)`
	wb_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F}; // wb_insn[0] must be 1
`else if (!wb_freeze) begin`	`else if (!wb_freeze) begin`
`wb_insn <= #1 ex_insn;`	`wb_insn <= #1 ex_insn;`
`end`	`end`
`end`	`end`