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Line 43... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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| Line 118... |
Line 121... |
assign scanb_so = scanb_si;
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assign scanb_so = scanb_si;
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`endif
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`endif
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`else
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`else
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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wire scanb_ram0_so;
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wire scanb_ram1_so;
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wire scanb_ram2_so;
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wire scanb_ram3_so;
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wire scanb_ram0_si = scanb_si;
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wire scanb_ram1_si = scanb_ram0_so;
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wire scanb_ram2_si = scanb_ram1_so;
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wire scanb_ram3_si = scanb_ram2_so;
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assign scanb_so = scanb_ram3_so;
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`endif
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//
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// Instantiation of RAM block 0
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//
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`ifdef OR1200_DC_1W_4KB
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or1200_spram_1024x8 dc_ram0(
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`endif
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`ifdef OR1200_DC_1W_8KB
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or1200_spram_2048x8 dc_ram0(
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`endif
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_ram0_si),
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.scanb_so(scanb_ram0_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.clk(clk),
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.rst(rst),
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.ce(en),
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.we(we[0]),
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.oe(1'b1),
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.addr(addr),
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.di(datain[7:0]),
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.do(dataout[7:0])
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);
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//
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// Instantiation of RAM block 1
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//
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`ifdef OR1200_DC_1W_4KB
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or1200_spram_1024x8 dc_ram1(
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`endif
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`ifdef OR1200_DC_1W_8KB
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or1200_spram_2048x8 dc_ram1(
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`endif
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_ram1_si),
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.scanb_so(scanb_ram1_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.clk(clk),
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.rst(rst),
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.ce(en),
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.we(we[1]),
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.oe(1'b1),
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.addr(addr),
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.di(datain[15:8]),
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.do(dataout[15:8])
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);
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//
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//
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// Instantiation of RAM block 2
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// Instantiation of RAM block
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//
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//
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`ifdef OR1200_DC_1W_4KB
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`ifdef OR1200_DC_1W_4KB
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or1200_spram_1024x8 dc_ram2(
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or1200_spram_1024x32_bw dc_ram(
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`endif
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`endif
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`ifdef OR1200_DC_1W_8KB
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`ifdef OR1200_DC_1W_8KB
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or1200_spram_2048x8 dc_ram2(
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or1200_spram_2048x32_bw dc_ram(
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`endif
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`endif
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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// RAM BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_ram2_si),
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.scanb_si(scanb_si),
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.scanb_so(scanb_ram2_so),
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.scanb_so(scanb_so),
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.scanb_en(scanb_en),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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.scanb_clk(scanb_clk),
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`endif
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`endif
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.clk(clk),
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.clk(clk),
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.rst(rst),
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.rst(rst),
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.ce(en),
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.ce(en),
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.we(we[2]),
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.we(we),
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.oe(1'b1),
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.oe(1'b1),
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.addr(addr),
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.addr(addr),
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.di(datain[23:16]),
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.di(datain),
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.do(dataout[23:16])
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.do(dataout)
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);
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);
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//
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// Instantiation of RAM block 3
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//
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`ifdef OR1200_DC_1W_4KB
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or1200_spram_1024x8 dc_ram3(
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`endif
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`endif
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`ifdef OR1200_DC_1W_8KB
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or1200_spram_2048x8 dc_ram3(
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`endif
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`ifdef OR1200_BIST
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// RAM BIST
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.scanb_rst(scanb_rst),
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.scanb_si(scanb_ram3_si),
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.scanb_so(scanb_ram3_so),
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.clk(clk),
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.rst(rst),
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.ce(en),
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.we(we[3]),
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.oe(1'b1),
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.addr(addr),
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.di(datain[31:24]),
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.do(dataout[31:24])
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);
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`endif
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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