URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [tags/] [rel_13/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 994 and 1022

Rev 994	Rev 1022
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.21 2002/08/22 02:18:55 lampret`
	`// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.`
	`//`
`// Revision 1.20 2002/08/18 21:59:45 lampret`	`// Revision 1.20 2002/08/18 21:59:45 lampret`
`// Disable SB until it is tested`	`// Disable SB until it is tested`
`//`	`//`
`// Revision 1.19 2002/08/18 19:53:08 lampret`	`// Revision 1.19 2002/08/18 19:53:08 lampret`
`// Added store buffer.`	`// Added store buffer.`
Line 324...	Line 327...
`// _Synopsys_ synthesis tool`	`// _Synopsys_ synthesis tool`
`//`	`//`
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES	//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES

`//`	`//`
	`// Enables default statement in some case blocks`
	`// and disables Synopsys synthesis directive full_case`
	`//`
	`// By default it is enabled. When disabled it`
	`// can increase clock frequency.`
	`//`
	`define OR1200_CASE_DEFAULT

	`//`
`// Operand width / register file address width`	`// Operand width / register file address width`
`//`	`//`
`// (DO NOT CHANGE)`	`// (DO NOT CHANGE)`
`//`	`//`
`define OR1200_OPERAND_WIDTH 32	`define OR1200_OPERAND_WIDTH 32