// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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wire dtlb_swe;
wire dtlb_swe;
wire dtlb_sre;
wire dtlb_sre;
wire[31:0] dtlb_dat_o;
wire[31:0] dtlb_dat_o;
wire dtlb_en;
wire dtlb_en;
wire dtlb_ci;
wire dtlb_ci;
reg dtlb_done;
wire fault;
wire fault;
wire miss;
wire miss;
`ifdef OR1200_NO_DMMU
`else
reg dtlb_done;
reg[31:`OR1200_DMMU_PS] dcpu_vpn_r;
reg[31:`OR1200_DMMU_PS] dcpu_vpn_r;
`endif
//
//
// Implemented bits inside match and translate registers
// Implemented bits inside match and translate registers
