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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/03/29 15:16:55 lampret
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// Some of the warnings fixed.
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//
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Revision 1.3 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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Line 99... |
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// Internal i/f
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// Internal i/f
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multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
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multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
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lsu_unstall, du_stall, mac_stall,
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lsu_unstall, du_stall, mac_stall,
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force_dslot_fetch, abort_ex,
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force_dslot_fetch, abort_ex,
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genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze
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genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
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icpu_ack_i, icpu_err_i
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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Line 123... |
output genpc_freeze;
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output genpc_freeze;
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output if_freeze;
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output if_freeze;
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output id_freeze;
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output id_freeze;
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output ex_freeze;
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output ex_freeze;
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output wb_freeze;
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output wb_freeze;
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input icpu_ack_i;
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input icpu_err_i;
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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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wire multicycle_freeze;
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wire multicycle_freeze;
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reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
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reg [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle_cnt;
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reg flushpipe_r;
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//
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//
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// Pipeline freeze
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// Pipeline freeze
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//
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//
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// Rules how to create freeze signals:
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// Rules how to create freeze signals:
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Line 146... |
//
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//
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// 2. Inserting NOPs in the middle of pipeline only if supported:
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// 2. Inserting NOPs in the middle of pipeline only if supported:
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// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
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// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
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// This way NOP is asserted from stage ID into EX stage.
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// This way NOP is asserted from stage ID into EX stage.
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//
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//
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assign genpc_freeze = du_stall | flushpipe;
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assign genpc_freeze = du_stall | flushpipe_r;
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assign if_freeze = id_freeze | extend_flush;
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assign if_freeze = id_freeze | extend_flush;
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//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
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//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
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assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall;
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assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall;
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assign ex_freeze = wb_freeze;
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assign ex_freeze = wb_freeze;
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//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
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//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
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assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
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assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
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//
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//
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// registered flushpipe
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//
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always @(posedge clk or posedge rst)
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if (rst)
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flushpipe_r <= #1 1'b0;
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else if (icpu_ack_i | icpu_err_i)
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// else if (!if_stall)
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flushpipe_r <= #1 flushpipe;
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else if (!flushpipe)
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flushpipe_r <= #1 1'b0;
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//
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// Multicycle freeze
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// Multicycle freeze
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//
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//
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assign multicycle_freeze = |multicycle_cnt;
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assign multicycle_freeze = |multicycle_cnt;
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//
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//
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