URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [tags/] [rel_13/] [or1200/] [rtl/] [verilog/] [or1200_gmultp2_32x32.v] - Diff between revs 504 and 916
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 504 |
Rev 916 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
|
//
|
// Revision 1.4 2001/12/04 05:02:35 lampret
|
// Revision 1.4 2001/12/04 05:02:35 lampret
|
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
|
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
|
//
|
//
|
// Revision 1.3 2001/10/21 17:57:16 lampret
|
// Revision 1.3 2001/10/21 17:57:16 lampret
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
|
| Line 86... |
Line 89... |
input RST;
|
input RST;
|
output [`OR1200_WW-1:0] P;
|
output [`OR1200_WW-1:0] P;
|
|
|
reg [`OR1200_WW-1:0] p0;
|
reg [`OR1200_WW-1:0] p0;
|
reg [`OR1200_WW-1:0] p1;
|
reg [`OR1200_WW-1:0] p1;
|
|
integer xi;
|
|
integer yi;
|
|
|
|
//
|
|
// Conversion unsigned to signed
|
|
//
|
|
always @(X)
|
|
xi <= X;
|
|
|
|
//
|
|
// Conversion unsigned to signed
|
|
//
|
|
always @(Y)
|
|
yi <= Y;
|
|
|
|
//
|
|
// First multiply stage
|
|
//
|
always @(posedge CLK or posedge RST)
|
always @(posedge CLK or posedge RST)
|
if (RST)
|
if (RST)
|
p0 <= `OR1200_WW'b0;
|
p0 <= `OR1200_WW'b0;
|
else
|
else
|
p0 <= #1 X * Y;
|
p0 <= #1 xi * yi;
|
|
|
|
//
|
|
// Second multiply stage
|
|
//
|
always @(posedge CLK or posedge RST)
|
always @(posedge CLK or posedge RST)
|
if (RST)
|
if (RST)
|
p1 <= `OR1200_WW'b0;
|
p1 <= `OR1200_WW'b0;
|
else
|
else
|
p1 <= #1 p0;
|
p1 <= #1 p0;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.