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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// OR1200's instruction fetch ////
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//// OR1200's instruction fetch ////
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//// ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// This file is part of the OpenRISC 1200 project ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.10 2001/11/20 18:46:15 simons
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// Revision 1.10 2001/11/20 18:46:15 simons
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// Break point bug fixed
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// Break point bug fixed
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//
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//
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// Revision 1.9 2001/11/18 09:58:28 lampret
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// Revision 1.9 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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// Fixed some l.trap typos.
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// External i/f to IC
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// External i/f to IC
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
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// Internal i/f
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// Internal i/f
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if_freeze, if_insn, if_pc, flushpipe,
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if_freeze, if_insn, if_pc, flushpipe,
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if_stall, has_dslot, taken, genpc_refetch, rfe,
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if_stall, no_more_dslot, taken, genpc_refetch, rfe,
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except_itlbmiss, except_immufault, except_ibuserr
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except_itlbmiss, except_immufault, except_ibuserr
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);
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);
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//
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//
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// I/O
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// I/O
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input if_freeze;
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input if_freeze;
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output [31:0] if_insn;
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output [31:0] if_insn;
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output [31:0] if_pc;
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output [31:0] if_pc;
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input flushpipe;
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input flushpipe;
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output if_stall;
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output if_stall;
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input has_dslot;
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input no_more_dslot;
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input taken;
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input taken;
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output genpc_refetch;
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output genpc_refetch;
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input rfe;
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input rfe;
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output except_itlbmiss;
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output except_itlbmiss;
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output except_immufault;
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output except_immufault;
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reg saved;
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reg saved;
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//
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//
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// IF stage insn
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// IF stage insn
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//
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//
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assign if_insn = icpu_err_i | has_dslot & taken | rfe ? {`OR1200_OR32_NOP, 26'h000_444F} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h000_666F};
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assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
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assign if_pc = saved ? addr_saved : icpu_adr_i;
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assign if_pc = saved ? addr_saved : icpu_adr_i;
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// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
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assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
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assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
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assign genpc_refetch = saved & icpu_ack_i;
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assign genpc_refetch = saved & icpu_ack_i;
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assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
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assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
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assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
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assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
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assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
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assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
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//
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//
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// Flag for saved insn/address
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// Flag for saved insn/address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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//
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//
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// Store fetched instruction
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// Store fetched instruction
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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else if (flushpipe)
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else if (flushpipe)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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else if (icpu_ack_i & if_freeze & !saved)
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else if (icpu_ack_i & if_freeze & !saved)
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insn_saved <= #1 icpu_dat_i;
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insn_saved <= #1 icpu_dat_i;
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else if (!if_freeze)
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else if (!if_freeze)
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
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insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
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//
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//
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// Store fetched instruction's address
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// Store fetched instruction's address
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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