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https://opencores.org/ocsvn/or1k/or1k/trunk
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Rev 1083 |
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/08/22 02:18:55 lampret
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// Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.
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//
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// Revision 1.1 2002/08/18 19:53:08 lampret
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// Revision 1.1 2002/08/18 19:53:08 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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//
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//
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input clk_i; // Clock
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input clk_i; // Clock
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input rst_i; // Reset
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input rst_i; // Reset
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input [dw-1:0] dat_i; // Input data bus
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input [dw-1:0] dat_i; // Input data bus
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input wr_i; // Write request
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input wr_i; // Write request
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input rd_i; // Read request
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input rd_i; // Read request
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output dat_o; // Output data bus
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output [dw-1:0] dat_o; // Output data bus
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output full_o; // FIFO full
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output full_o; // FIFO full
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output empty_o;// FIFO empty
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output empty_o;// FIFO empty
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//
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//
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// Internal regs
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// Internal regs
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//
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//
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reg [dw:0] mem [fl-1:0];
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reg [dw-1:0] mem [fl-1:0];
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reg [dw-1:0] dat_o;
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reg [dw-1:0] dat_o;
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reg [fw+1:0] cntr;
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reg [fw+1:0] cntr;
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reg [fw-1:0] wr_pntr;
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reg [fw-1:0] wr_pntr;
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reg [fw-1:0] rd_pntr;
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reg [fw-1:0] rd_pntr;
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reg empty_o;
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reg empty_o;
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