URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 504 |
Rev 562 |
| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
|
//
|
// Revision 1.9 2001/10/21 17:57:16 lampret
|
// Revision 1.9 2001/10/21 17:57:16 lampret
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
|
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
|
//
|
//
|
// Revision 1.8 2001/10/19 23:28:46 lampret
|
// Revision 1.8 2001/10/19 23:28:46 lampret
|
// Fixed some synthesis warnings. Configured with caches and MMUs.
|
// Fixed some synthesis warnings. Configured with caches and MMUs.
|
| Line 190... |
Line 193... |
state <= #1 `OR1200_ICFSM_DOLOAD;
|
state <= #1 `OR1200_ICFSM_DOLOAD;
|
saved_addr <= #1 start_addr;
|
saved_addr <= #1 start_addr;
|
hitmiss_eval <= #1 1'b1;
|
hitmiss_eval <= #1 1'b1;
|
load <= #1 1'b1;
|
load <= #1 1'b1;
|
end
|
end
|
|
else if (!icimmu_cyc_i | !icimmu_stb_i) begin // load aborted (usually caused by exception)
|
|
state <= #1 `OR1200_ICFSM_IDLE;
|
|
hitmiss_eval <= #1 1'b0;
|
|
load <= #1 1'b0;
|
|
end
|
else // load in-progress
|
else // load in-progress
|
hitmiss_eval <= #1 1'b0;
|
hitmiss_eval <= #1 1'b0;
|
`OR1200_ICFSM_LREFILL3 : begin
|
`OR1200_ICFSM_LREFILL3 : begin
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
if (biudata_valid && (|cnt)) begin // refill ack, more loads to come
|
cnt <= #1 cnt - 'd1;
|
cnt <= #1 cnt - 'd1;
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.