Subversion Repositories or1k

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.4  2002/03/29 15:16:53  lampret

// Revision 1.4  2002/03/29 15:16:53  lampret

// Some of the warnings fixed.

// Some of the warnings fixed.

//

//

// Revision 1.3  2002/01/28 01:15:59  lampret

// Revision 1.3  2002/01/28 01:15:59  lampret

// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.

// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.

reg     [width-1:0]              result;

reg     [width-1:0]              result;

reg     [width-1:0]              shifted_rotated;

reg     [width-1:0]              shifted_rotated;

reg                             flagforw;

reg                             flagforw;

reg                             flagcomp;

reg                             flagcomp;

reg                             flag_we;

reg                             flag_we;

`ifdef OR1200_SIM_ALU_DIV

`ifdef OR1200_SIM_ALU_DIV

integer                         d1;

integer                         d1;

integer                         d2;

integer                         d2;

`endif

`endif

wire    [width-1:0]              comp_a;

wire    [width-1:0]              comp_a;

wire    [width-1:0]              comp_b;

wire    [width-1:0]              comp_b;

`ifdef OR1200_IMPL_ALU_COMP1

`ifdef OR1200_IMPL_ALU_COMP1

wire                            a_eq_b;

wire                            a_eq_b;

wire                            a_lt_b;

wire                            a_lt_b;