| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2002/10/28 11:09:52 igorm
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// OR1200_ASIC is automatically switched on if the fpga define is turned on in the marvin_top_defines.c
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//
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// Revision 1.4 2002/10/24 17:38:16 igorm
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// Define OR1200_BIST switched on.
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//
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Removed obsolete comment.
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// Removed obsolete comment.
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//
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//
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// Revision 1.26 2002/09/08 05:52:16 lampret
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// Revision 1.26 2002/09/08 05:52:16 lampret
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// Added optional l.div/l.divu insns. By default they are disabled.
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// Added optional l.div/l.divu insns. By default they are disabled.
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| Line 182... |
Line 191... |
// Revision 1.1 2001/07/20 00:46:03 lampret
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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// Development version of RTL. Libraries are missing.
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//
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//
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//
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//
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|
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`include "marvin_top_defines.v"
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//
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//
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// Dump VCD
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// Dump VCD
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//
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//
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//`define OR1200_VCD_DUMP
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//`define OR1200_VCD_DUMP
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//
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//
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// Generate debug messages during simulation
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// Generate debug messages during simulation
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//
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//
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//`define OR1200_VERBOSE
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//`define OR1200_VERBOSE
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//`define OR1200_ASIC
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`ifdef fpga
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`else
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`define OR1200_ASIC
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`endif
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////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////
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//
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//
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// Typical configuration for an ASIC
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// Typical configuration for an ASIC
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//
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//
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`ifdef OR1200_ASIC
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`ifdef OR1200_ASIC
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| Line 206... |
Line 221... |
//
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//
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//`define OR1200_ARTISAN_SSP
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//`define OR1200_ARTISAN_SSP
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//`define OR1200_ARTISAN_SDP
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//`define OR1200_ARTISAN_SDP
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//`define OR1200_ARTISAN_STP
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//`define OR1200_ARTISAN_STP
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`define OR1200_VIRTUALSILICON_SSP
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`define OR1200_VIRTUALSILICON_SSP
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`define OR1200_VIRTUALSILICON_STP_T1
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//`define OR1200_VIRTUALSILICON_STP_T1
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//`define OR1200_VIRTUALSILICON_STP_T2
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//`define OR1200_VIRTUALSILICON_STP_T2
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|
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//
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//
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// Do not implement Data cache
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// Do not implement Data cache
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//
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//
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| Line 311... |
Line 326... |
// At the moment this only works for Virtual Silicon
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// At the moment this only works for Virtual Silicon
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// single port RAMs. For other RAMs it has not effect.
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// single port RAMs. For other RAMs it has not effect.
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// Special wrapper for VS RAMs needs to be provided
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// Special wrapper for VS RAMs needs to be provided
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// with scan flops to facilitate bist scan.
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// with scan flops to facilitate bist scan.
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//
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//
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//`define OR1200_BIST
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`define OR1200_BIST
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|
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//
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//
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// Register OR1200 WISHBONE outputs
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// Register OR1200 WISHBONE outputs
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// (must be defined/enabled)
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// (must be defined/enabled)
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//
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//
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