| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.30 2002/10/28 15:09:22 mohor
|
|
// Previous check-in was done by mistake.
|
|
//
|
// Revision 1.29 2002/10/28 15:03:50 mohor
|
// Revision 1.29 2002/10/28 15:03:50 mohor
|
// Signal scanb_sen renamed to scanb_en.
|
// Signal scanb_sen renamed to scanb_en.
|
//
|
//
|
// Revision 1.28 2002/10/17 20:04:40 lampret
|
// Revision 1.28 2002/10/17 20:04:40 lampret
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
| Line 353... |
Line 356... |
// undefine this macro.
|
// undefine this macro.
|
//
|
//
|
//`define OR1200_WB_RETRY 7
|
//`define OR1200_WB_RETRY 7
|
|
|
//
|
//
|
|
// WISHBONE Consecutive Address Burst
|
|
//
|
|
// This was used prior to WISHBONE B3 specification
|
|
// to identify bursts. It is no longer needed but
|
|
// remains enabled for compatibility with old designs.
|
|
//
|
|
// To remove *wb_cab_o ports undefine this macro.
|
|
//
|
|
`define OR1200_WB_CAB
|
|
|
|
//
|
|
// WISHBONE B3 compatible interface
|
|
//
|
|
// This follows the WISHBONE B3 specification.
|
|
// It is not enabled by default because most
|
|
// designs still don't use WB b3.
|
|
//
|
|
// To enable *wb_cti_o/*wb_bte_o ports,
|
|
// define this macro.
|
|
//
|
|
//`define OR1200_WB_B3
|
|
|
|
//
|
// Enable additional synthesis directives if using
|
// Enable additional synthesis directives if using
|
// _Synopsys_ synthesis tool
|
// _Synopsys_ synthesis tool
|
//
|
//
|
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
|
|
