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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.35 2003/04/24 00:16:07 lampret
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// No functional changes. Added defines to disable implementation of multiplier/MAC
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//
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// Revision 1.34 2003/04/20 22:23:57 lampret
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// Revision 1.34 2003/04/20 22:23:57 lampret
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// No functional change. Only added customization for exception vectors.
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// No functional change. Only added customization for exception vectors.
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//
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//
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// Revision 1.33 2003/04/07 20:56:07 lampret
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// Revision 1.33 2003/04/07 20:56:07 lampret
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
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// Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description.
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//
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//
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// Revision 1.30 2002/10/28 15:09:22 mohor
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// Revision 1.30 2002/10/28 15:09:22 mohor
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// Previous check-in was done by mistake.
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// Previous check-in was done by mistake.
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//
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//
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Revision 1.29 2002/10/28 15:03:50 mohor
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// Signal scanb_sen renamed to scanb_en.
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// Signal mbist_sen renamed to mbist_ctrl_i.
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//
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//
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Revision 1.28 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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//
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Revision 1.27 2002/09/16 03:13:23 lampret
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// Special wrapper for VS RAMs needs to be provided
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// Special wrapper for VS RAMs needs to be provided
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// with scan flops to facilitate bist scan.
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// with scan flops to facilitate bist scan.
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//
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//
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//`define OR1200_BIST
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//`define OR1200_BIST
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// width of MBIST control bus
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`define OR1200_MBIST_CTRL_WIDTH 3
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//
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//
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// Register OR1200 WISHBONE outputs
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// Register OR1200 WISHBONE outputs
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// (must be defined/enabled)
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// (must be defined/enabled)
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//
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//
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`define OR1200_REGISTERED_OUTPUTS
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`define OR1200_REGISTERED_OUTPUTS
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