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[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 790 and 870

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Rev 790	Rev 870
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.14 2002/03/29 16:24:06 lampret`
	`// Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives`
	`//`
`// Revision 1.13 2002/03/29 15:16:55 lampret`	`// Revision 1.13 2002/03/29 15:16:55 lampret`
`// Some of the warnings fixed.`	`// Some of the warnings fixed.`
`//`	`//`
`// Revision 1.12 2002/03/28 19:25:42 lampret`	`// Revision 1.12 2002/03/28 19:25:42 lampret`
`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`	`// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.`
Line 323...	Line 326...
//`define OR1200_CLKDIV_4_SUPPORTED	//`define OR1200_CLKDIV_4_SUPPORTED

`//`	`//`
`// Type of register file RAM`	`// Type of register file RAM`
`//`	`//`
	`// Memory macro w/ two ports (see or1200_hdtp_32x32.v)`
// `define OR1200_RFRAM_TWOPORT	// `define OR1200_RFRAM_TWOPORT
	`//`
	`// Memory macro dual port (see or1200_hddp_32x32.v)`
	`define OR1200_RFRAM_DUALPORT
	`//`
	`// ... otherwise generic (flip-flop based) register file`

`//`	`//`
`// Type of mem2reg aligner to implement.`	`// Type of mem2reg aligner to implement.`
`//`	`//`
`// Once OR1200_IMPL_MEM2REG2 yielded faster`	`// Once OR1200_IMPL_MEM2REG2 yielded faster`

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[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Diff between revs 790 and 870