| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.6 2002/03/28 19:10:40 lampret
|
|
// Optimized cache controller FSM.
|
|
//
|
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
|
// Revision 1.1.1.1 2002/03/21 16:55:45 lampret
|
// First import of the "new" XESS XSV environment.
|
// First import of the "new" XESS XSV environment.
|
//
|
//
|
//
|
//
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
// Revision 1.5 2002/02/11 04:33:17 lampret
|
| Line 86... |
Line 89... |
// synopsys translate_off
|
// synopsys translate_off
|
`include "timescale.v"
|
`include "timescale.v"
|
// synopsys translate_on
|
// synopsys translate_on
|
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
`define OR1200_ICFSM_IDLE 3'd0
|
`define OR1200_ICFSM_IDLE 2'd0
|
`define OR1200_ICFSM_CFETCH 3'd1
|
`define OR1200_ICFSM_CFETCH 2'd1
|
`define OR1200_ICFSM_LREFILL3 3'd2
|
`define OR1200_ICFSM_LREFILL3 2'd2
|
`define OR1200_ICFSM_IFETCH 3'd3
|
`define OR1200_ICFSM_IFETCH 2'd3
|
|
|
//
|
//
|
// Data cache FSM for cache line of 16 bytes (4x singleword)
|
// Data cache FSM for cache line of 16 bytes (4x singleword)
|
//
|
//
|
|
|
module or1200_ic_fsm(
|
module or1200_ic_fsm(
|
// Clock and reset
|
// Clock and reset
|
clk, rst,
|
clk, rst,
|
|
|
// Internal i/f to top level IC
|
// Internal i/f to top level IC
|
ic_en, icimmu_cycstb_i, icimmu_ci_i, icpu_sel_i,
|
ic_en, icimmu_cycstb_i, icimmu_ci_i,
|
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
|
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
|
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
|
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
|
burst, tag_we
|
burst, tag_we
|
);
|
);
|
|
|
| Line 114... |
Line 117... |
input clk;
|
input clk;
|
input rst;
|
input rst;
|
input ic_en;
|
input ic_en;
|
input icimmu_cycstb_i;
|
input icimmu_cycstb_i;
|
input icimmu_ci_i;
|
input icimmu_ci_i;
|
input [3:0] icpu_sel_i;
|
|
input tagcomp_miss;
|
input tagcomp_miss;
|
input biudata_valid;
|
input biudata_valid;
|
input biudata_error;
|
input biudata_error;
|
input [31:0] start_addr;
|
input [31:0] start_addr;
|
output [31:0] saved_addr;
|
output [31:0] saved_addr;
|
| Line 132... |
Line 134... |
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
reg [31:0] saved_addr_r;
|
reg [31:0] saved_addr_r;
|
reg [2:0] state;
|
reg [1:0] state;
|
reg [2:0] cnt;
|
reg [2:0] cnt;
|
reg hitmiss_eval;
|
reg hitmiss_eval;
|
reg load;
|
reg load;
|
reg cache_inhibit;
|
reg cache_inhibit;
|
|
|
