| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/03/29 15:16:56 lampret
|
|
// Some of the warnings fixed.
|
|
//
|
// Revision 1.3 2002/03/28 19:14:10 lampret
|
// Revision 1.3 2002/03/28 19:14:10 lampret
|
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
|
// Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2
|
//
|
//
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
| Line 204... |
Line 207... |
//
|
//
|
// Byte 0
|
// Byte 0
|
//
|
//
|
always @(sel_byte0 or memdata) begin
|
always @(sel_byte0 or memdata) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte0) // synopsys parallel_case infer_mux
|
|
`else
|
case(sel_byte0) // synopsys full_case parallel_case infer_mux
|
case(sel_byte0) // synopsys full_case parallel_case infer_mux
|
|
`endif
|
|
`else
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte0) // synopsys parallel_case
|
`else
|
`else
|
case(sel_byte0) // synopsys full_case parallel_case
|
case(sel_byte0) // synopsys full_case parallel_case
|
`endif
|
`endif
|
|
`endif
|
`OR1200_M2R_BYTE0: begin
|
`OR1200_M2R_BYTE0: begin
|
regdata_ll = memdata[7:0];
|
regdata_ll = memdata[7:0];
|
end
|
end
|
`OR1200_M2R_BYTE1: begin
|
`OR1200_M2R_BYTE1: begin
|
regdata_ll = memdata[15:8];
|
regdata_ll = memdata[15:8];
|
end
|
end
|
`OR1200_M2R_BYTE2: begin
|
`OR1200_M2R_BYTE2: begin
|
regdata_ll = memdata[23:16];
|
regdata_ll = memdata[23:16];
|
end
|
end
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
default: begin
|
|
`else
|
`OR1200_M2R_BYTE3: begin
|
`OR1200_M2R_BYTE3: begin
|
|
`endif
|
regdata_ll = memdata[31:24];
|
regdata_ll = memdata[31:24];
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Byte 1
|
// Byte 1
|
//
|
//
|
always @(sel_byte1 or memdata) begin
|
always @(sel_byte1 or memdata) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte1) // synopsys parallel_case infer_mux
|
|
`else
|
case(sel_byte1) // synopsys full_case parallel_case infer_mux
|
case(sel_byte1) // synopsys full_case parallel_case infer_mux
|
|
`endif
|
|
`else
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte1) // synopsys parallel_case
|
`else
|
`else
|
case(sel_byte1) // synopsys full_case parallel_case
|
case(sel_byte1) // synopsys full_case parallel_case
|
`endif
|
`endif
|
|
`endif
|
`OR1200_M2R_ZERO: begin
|
`OR1200_M2R_ZERO: begin
|
regdata_lh = 8'h00;
|
regdata_lh = 8'h00;
|
end
|
end
|
`OR1200_M2R_BYTE1: begin
|
`OR1200_M2R_BYTE1: begin
|
regdata_lh = memdata[15:8];
|
regdata_lh = memdata[15:8];
|
| Line 250... |
Line 273... |
regdata_lh = {8{memdata[15]}};
|
regdata_lh = {8{memdata[15]}};
|
end
|
end
|
`OR1200_M2R_EXTB2: begin
|
`OR1200_M2R_EXTB2: begin
|
regdata_lh = {8{memdata[23]}};
|
regdata_lh = {8{memdata[23]}};
|
end
|
end
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
default: begin
|
|
`else
|
`OR1200_M2R_EXTB3: begin
|
`OR1200_M2R_EXTB3: begin
|
|
`endif
|
regdata_lh = {8{memdata[31]}};
|
regdata_lh = {8{memdata[31]}};
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Byte 2
|
// Byte 2
|
//
|
//
|
always @(sel_byte2 or memdata) begin
|
always @(sel_byte2 or memdata) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte2) // synopsys parallel_case infer_mux
|
|
`else
|
case(sel_byte2) // synopsys full_case parallel_case infer_mux
|
case(sel_byte2) // synopsys full_case parallel_case infer_mux
|
|
`endif
|
|
`else
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte2) // synopsys parallel_case
|
`else
|
`else
|
case(sel_byte2) // synopsys full_case parallel_case
|
case(sel_byte2) // synopsys full_case parallel_case
|
`endif
|
`endif
|
|
`endif
|
`OR1200_M2R_ZERO: begin
|
`OR1200_M2R_ZERO: begin
|
regdata_hl = 8'h00;
|
regdata_hl = 8'h00;
|
end
|
end
|
`OR1200_M2R_BYTE2: begin
|
`OR1200_M2R_BYTE2: begin
|
regdata_hl = memdata[23:16];
|
regdata_hl = memdata[23:16];
|
| Line 280... |
Line 315... |
regdata_hl = {8{memdata[15]}};
|
regdata_hl = {8{memdata[15]}};
|
end
|
end
|
`OR1200_M2R_EXTB2: begin
|
`OR1200_M2R_EXTB2: begin
|
regdata_hl = {8{memdata[23]}};
|
regdata_hl = {8{memdata[23]}};
|
end
|
end
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
default: begin
|
|
`else
|
`OR1200_M2R_EXTB3: begin
|
`OR1200_M2R_EXTB3: begin
|
|
`endif
|
regdata_hl = {8{memdata[31]}};
|
regdata_hl = {8{memdata[31]}};
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
// Byte 3
|
// Byte 3
|
//
|
//
|
always @(sel_byte3 or memdata) begin
|
always @(sel_byte3 or memdata) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte3) // synopsys parallel_case infer_mux
|
|
`else
|
case(sel_byte3) // synopsys full_case parallel_case infer_mux
|
case(sel_byte3) // synopsys full_case parallel_case infer_mux
|
|
`endif
|
|
`else
|
|
`ifdef OR1200_CASE_DEFAULT
|
|
case(sel_byte3) // synopsys parallel_case
|
`else
|
`else
|
case(sel_byte3) // synopsys full_case parallel_case
|
case(sel_byte3) // synopsys full_case parallel_case
|
`endif
|
`endif
|
|
`endif
|
`OR1200_M2R_ZERO: begin
|
`OR1200_M2R_ZERO: begin
|
regdata_hh = 8'h00;
|
regdata_hh = 8'h00;
|
end
|
end
|
`OR1200_M2R_BYTE3: begin
|
`OR1200_M2R_BYTE3: begin
|
regdata_hh = memdata[31:24];
|
regdata_hh = memdata[31:24];
|
| Line 310... |
Line 357... |
regdata_hh = {8{memdata[15]}};
|
regdata_hh = {8{memdata[15]}};
|
end
|
end
|
`OR1200_M2R_EXTB2: begin
|
`OR1200_M2R_EXTB2: begin
|
regdata_hh = {8{memdata[23]}};
|
regdata_hh = {8{memdata[23]}};
|
end
|
end
|
|
`ifdef OR1200_CASE_DEFAULT
|
`OR1200_M2R_EXTB3: begin
|
`OR1200_M2R_EXTB3: begin
|
|
`else
|
|
`OR1200_M2R_EXTB3: begin
|
|
`endif
|
regdata_hh = {8{memdata[31]}};
|
regdata_hh = {8{memdata[31]}};
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
| Line 330... |
Line 381... |
//
|
//
|
// Alignment
|
// Alignment
|
//
|
//
|
always @(addr or memdata) begin
|
always @(addr or memdata) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
case(addr) // synopsys infer_mux
|
case(addr) // synopsys parallel_case infer_mux
|
`else
|
`else
|
case(addr) // synopsys full_case parallel_case
|
case(addr) // synopsys parallel_case
|
`endif
|
`endif
|
2'b00:
|
2'b00:
|
aligned = memdata;
|
aligned = memdata;
|
2'b01:
|
2'b01:
|
aligned = {memdata[23:0], 8'b0};
|
aligned = {memdata[23:0], 8'b0};
|
| Line 350... |
Line 401... |
//
|
//
|
// Bytes
|
// Bytes
|
//
|
//
|
always @(lsu_op or aligned) begin
|
always @(lsu_op or aligned) begin
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
|
case(lsu_op) // synopsys infer_mux
|
case(lsu_op) // synopsys parallel_case infer_mux
|
`else
|
`else
|
case(lsu_op) // synopsys parallel_case
|
case(lsu_op) // synopsys parallel_case
|
`endif
|
`endif
|
`OR1200_LSUOP_LBZ: begin
|
`OR1200_LSUOP_LBZ: begin
|
regdata[7:0] = aligned[31:24];
|
regdata[7:0] = aligned[31:24];
|
