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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Revision 1.9 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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//
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Revision 1.8 2001/10/19 23:28:46 lampret
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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// Fixed some synthesis warnings. Configured with caches and MMUs.
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| Line 85... |
Line 88... |
//
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//
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// Faster implementation of mem2reg
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// Faster implementation of mem2reg
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//
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//
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`ifdef OR1200_MEM2REG_FAST
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`ifdef OR1200_MEM2REG_FAST
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`define OR1200_SEL_00 2'b00
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`define OR1200_M2R_BYTE0 4'b0000
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`define OR1200_SEL_01 2'b01
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`define OR1200_M2R_BYTE1 4'b0001
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`define OR1200_SEL_10 2'b10
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`define OR1200_M2R_BYTE2 4'b0010
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`define OR1200_SEL_11 2'b11
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`define OR1200_M2R_BYTE3 4'b0011
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`define OR1200_M2R_EXTB0 4'b0100
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`define OR1200_M2R_EXTB1 4'b0101
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`define OR1200_M2R_EXTB2 4'b0110
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`define OR1200_M2R_EXTB3 4'b0111
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`define OR1200_M2R_ZERO 4'b0000
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reg [7:0] regdata_hh;
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reg [7:0] regdata_hh;
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reg [7:0] regdata_hl;
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reg [7:0] regdata_hl;
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reg [7:0] regdata_lh;
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reg [7:0] regdata_lh;
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reg [7:0] regdata_ll;
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reg [7:0] regdata_ll;
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reg [width-1:0] aligned;
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reg [width-1:0] aligned;
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reg [1:0] sel_byte0, sel_byte1,
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reg [3:0] sel_byte0, sel_byte1,
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sel_byte2, sel_byte3;
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sel_byte2, sel_byte3;
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assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
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assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
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//
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//
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// Byte select 0
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// Byte select 0
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//
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//
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always @(addr or lsu_op) begin
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr})
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b01x, 2'b00}:
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{3'b01x, 2'b00}: // lbz/lbs 0
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sel_byte0 = `OR1200_SEL_11;
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sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
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{3'b01x, 2'b01}:
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{3'b01x, 2'b01}, // lbz/lbs 1
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sel_byte0 = `OR1200_SEL_10;
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{3'b10x, 2'b00}: // lhz/lhs 0
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{3'b01x, 2'b10}:
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sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
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sel_byte0 = `OR1200_SEL_01;
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{3'b01x, 2'b10}: // lbz/lbs 2
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{3'b01x, 2'b11}:
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sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
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sel_byte0 = `OR1200_SEL_00;
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default: // all other cases
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{3'b10x, 2'b00}:
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sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
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sel_byte0 = `OR1200_SEL_10;
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{3'b10x, 2'b10}:
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sel_byte0 = `OR1200_SEL_00;
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default:
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sel_byte0 = `OR1200_SEL_00;
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endcase
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endcase
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end
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end
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//
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//
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// Byte select 1
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// Byte select 1
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//
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//
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always @(addr or lsu_op) begin
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr})
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b010, 2'bxx}:
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{3'b010, 2'bxx}: // lbz
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sel_byte1 = `OR1200_SEL_00; // zero extend
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sel_byte1 = `OR1200_M2R_ZERO; // zero extend
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{3'b011, 2'bxx}:
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{3'b011, 2'b00}: // lbs 0
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sel_byte1 = `OR1200_SEL_10; // sign extend byte
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sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
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{3'b10x, 2'b00}:
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{3'b011, 2'b01}: // lbs 1
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sel_byte1 = `OR1200_SEL_11;
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sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
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default:
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{3'b011, 2'b10}: // lbs 2
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sel_byte1 = `OR1200_SEL_01;
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sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
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{3'b011, 2'b11}: // lbs 3
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sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
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{3'b10x, 2'b00}: // lhz/lhs 0
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sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
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default: // all other cases
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sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
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endcase
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endcase
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end
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end
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//
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//
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// Byte select 2
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// Byte select 2
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//
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//
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always @(addr or lsu_op) begin
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr})
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b010, 2'bxx},
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{3'b010, 2'bxx}, // lbz
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{3'b100, 2'bxx}:
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{3'b100, 2'bxx}: // lhz
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sel_byte2 = `OR1200_SEL_00; // zero extend
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sel_byte2 = `OR1200_M2R_ZERO; // zero extend
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{3'b011, 2'bxx}:
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{3'b011, 2'b00}, // lbs 0
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sel_byte2 = `OR1200_SEL_01; // sign extend byte
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{3'b101, 2'b00}: // lhs 0
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{3'b101, 2'bxx}:
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sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
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sel_byte2 = `OR1200_SEL_11; // sign extend halfword
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{3'b011, 2'b01}: // lbs 1
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default:
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sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
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sel_byte2 = `OR1200_SEL_10;
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{3'b011, 2'b10}, // lbs 2
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{3'b101, 2'b10}: // lhs 0
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sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
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{3'b011, 2'b11}: // lbs 3
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sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
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default: // all other cases
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sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
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endcase
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endcase
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end
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end
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//
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//
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// Byte select 3
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// Byte select 3
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//
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//
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always @(addr or lsu_op) begin
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always @(addr or lsu_op) begin
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casex({lsu_op[2:0], addr})
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casex({lsu_op[2:0], addr}) // synopsys parallel_case
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{3'b010, 2'bxx},
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{3'b010, 2'bxx}, // lbz
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{3'b100, 2'bxx}:
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{3'b100, 2'bxx}: // lhz
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sel_byte3 = `OR1200_SEL_00; // zero extend
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sel_byte3 = `OR1200_M2R_ZERO; // zero extend
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{3'b011, 2'bxx}:
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{3'b011, 2'b00}, // lbs 0
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sel_byte3 = `OR1200_SEL_01; // sign extend byte
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{3'b101, 2'b00}: // lhs 0
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{3'b101, 2'bxx}:
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sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
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sel_byte3 = `OR1200_SEL_10; // sign extend halfword
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{3'b011, 2'b01}: // lbs 1
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default:
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sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
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sel_byte3 = `OR1200_SEL_11;
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{3'b011, 2'b10}, // lbs 2
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{3'b101, 2'b10}: // lhs 0
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sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
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{3'b011, 2'b11}: // lbs 3
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sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
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default: // all other cases
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sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
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endcase
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endcase
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end
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end
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//
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//
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// Byte 0
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// Byte 0
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//
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//
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always @(sel_byte0 or memdata) begin
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always @(sel_byte0 or memdata) begin
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case(sel_byte0) // synopsys full_case parallel_case infer_mux
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case(sel_byte0) // synopsys full_case parallel_case infer_mux
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`OR1200_SEL_00: begin
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`OR1200_M2R_BYTE0: begin
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regdata_ll = memdata[7:0];
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regdata_ll = memdata[7:0];
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end
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end
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`OR1200_SEL_01: begin
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`OR1200_M2R_BYTE1: begin
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regdata_ll = memdata[15:8];
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regdata_ll = memdata[15:8];
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end
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end
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`OR1200_SEL_10: begin
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`OR1200_M2R_BYTE2: begin
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regdata_ll = memdata[23:16];
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regdata_ll = memdata[23:16];
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end
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end
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`OR1200_SEL_11: begin
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`OR1200_M2R_BYTE3: begin
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regdata_ll = memdata[31:24];
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regdata_ll = memdata[31:24];
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end
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end
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endcase
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endcase
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end
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end
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//
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//
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// Byte 1
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// Byte 1
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//
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//
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always @(sel_byte1 or memdata) begin
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always @(sel_byte1 or memdata) begin
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case(sel_byte1) // synopsys full_case parallel_case infer_mux
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case(sel_byte1) // synopsys full_case parallel_case infer_mux
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`OR1200_SEL_00: begin
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`OR1200_M2R_ZERO: begin
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regdata_lh = 8'b0;
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regdata_lh = 8'h00;
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end
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end
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`OR1200_SEL_01: begin
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`OR1200_M2R_BYTE1: begin
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regdata_lh = memdata[15:8];
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regdata_lh = memdata[15:8];
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end
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end
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`OR1200_SEL_10: begin
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`OR1200_M2R_BYTE3: begin
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regdata_lh = memdata[31:24];
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end
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`OR1200_M2R_EXTB0: begin
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regdata_lh = {8{memdata[7]}};
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regdata_lh = {8{memdata[7]}};
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end
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end
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`OR1200_SEL_11: begin
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`OR1200_M2R_EXTB1: begin
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regdata_lh = memdata[31:24];
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regdata_lh = {8{memdata[15]}};
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end
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`OR1200_M2R_EXTB2: begin
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regdata_lh = {8{memdata[23]}};
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end
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`OR1200_M2R_EXTB3: begin
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regdata_lh = {8{memdata[31]}};
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end
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end
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endcase
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endcase
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end
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end
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//
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//
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// Byte 2
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// Byte 2
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//
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//
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always @(sel_byte2 or memdata) begin
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always @(sel_byte2 or memdata) begin
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case(sel_byte2) // synopsys full_case parallel_case infer_mux
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case(sel_byte2) // synopsys full_case parallel_case infer_mux
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`OR1200_SEL_00: begin
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`OR1200_M2R_ZERO: begin
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regdata_hl = 8'b0;
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regdata_hl = 8'h00;
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end
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`OR1200_SEL_01: begin
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regdata_hl = {8{memdata[7]}};
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end
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end
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`OR1200_SEL_10: begin
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`OR1200_M2R_BYTE2: begin
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regdata_hl = memdata[23:16];
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regdata_hl = memdata[23:16];
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end
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end
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`OR1200_SEL_11: begin
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`OR1200_M2R_EXTB0: begin
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regdata_hl = {8{memdata[7]}};
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end
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`OR1200_M2R_EXTB1: begin
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regdata_hl = {8{memdata[15]}};
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regdata_hl = {8{memdata[15]}};
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end
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end
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`OR1200_M2R_EXTB2: begin
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regdata_hl = {8{memdata[23]}};
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end
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`OR1200_M2R_EXTB3: begin
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regdata_hl = {8{memdata[31]}};
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end
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endcase
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endcase
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end
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end
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//
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//
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// Byte 3
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// Byte 3
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//
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//
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always @(sel_byte3 or memdata) begin
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always @(sel_byte3 or memdata) begin
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case(sel_byte3) // synopsys full_case parallel_case infer_mux
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case(sel_byte3) // synopsys full_case parallel_case infer_mux
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`OR1200_SEL_00: begin
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`OR1200_M2R_ZERO: begin
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regdata_hh = 8'b0;
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regdata_hh = 8'h00;
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end
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end
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`OR1200_SEL_01: begin
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`OR1200_M2R_BYTE3: begin
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regdata_hh = memdata[31:24];
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end
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`OR1200_M2R_EXTB0: begin
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regdata_hh = {8{memdata[7]}};
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regdata_hh = {8{memdata[7]}};
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end
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end
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`OR1200_SEL_10: begin
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`OR1200_M2R_EXTB1: begin
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regdata_hh = {8{memdata[15]}};
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regdata_hh = {8{memdata[15]}};
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end
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end
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`OR1200_SEL_11: begin
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`OR1200_M2R_EXTB2: begin
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regdata_hh = memdata[31:24];
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regdata_hh = {8{memdata[23]}};
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end
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`OR1200_M2R_EXTB3: begin
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regdata_hh = {8{memdata[31]}};
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end
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end
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endcase
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endcase
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end
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end
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`else
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`else
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