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Line 61... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2003/04/07 01:19:07 lampret
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// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
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//
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// Revision 1.2 2002/10/17 20:04:40 lampret
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// Revision 1.2 2002/10/17 20:04:40 lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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Line 144... |
//
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//
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// Internal wires and registers
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// Internal wires and registers
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//
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//
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wire [3:0] unconnected;
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wire [3:0] unconnected;
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`ifdef OR1200_VIRTUALSILICON_SSP
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`else
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`ifdef OR1200_BIST
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`ifdef OR1200_BIST
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assign scanb_so = scanb_si;
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assign scanb_so = scanb_si;
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`endif
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`endif
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`endif
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`ifdef OR1200_ARTISAN_SSP
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`ifdef OR1200_ARTISAN_SSP
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//
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//
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// Instantiation of ASIC memory:
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// Instantiation of ASIC memory:
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Line 158... |
// Artisan Synchronous Single-Port RAM (ra1sh)
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// Artisan Synchronous Single-Port RAM (ra1sh)
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//
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//
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`ifdef UNUSED
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`ifdef UNUSED
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art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
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art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
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`else
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`else
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`ifdef OR1200_BIST
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art_hssp_512x20_bist artisan_ssp(
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`else
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art_hssp_512x20 artisan_ssp(
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art_hssp_512x20 artisan_ssp(
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`endif
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`endif
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.clk(clk),
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`endif
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.cen(~ce),
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`ifdef OR1200_BIST
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.wen(~we),
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// RAM BIST
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.a(addr),
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.scanb_rst(scanb_rst),
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.d(di),
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.scanb_si(scanb_si),
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.oen(~oe),
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.scanb_so(scanb_so),
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.q(do)
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.scanb_en(scanb_en),
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.scanb_clk(scanb_clk),
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`endif
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.CLK(clk),
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.CEN(~ce),
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.WEN(~we),
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.A(addr),
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.D(di),
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.OEN(~oe),
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.Q(do)
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);
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);
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`else
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`else
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`ifdef OR1200_AVANT_ATP
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`ifdef OR1200_AVANT_ATP
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