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[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 636 and 736

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[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Diff between revs 636 and 736

Rev 636	Rev 736
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2002/02/01 19:56:54 lampret`
	`// Fixed combinational loops.`
	`//`
`// Revision 1.4 2002/01/23 07:52:36 lampret`	`// Revision 1.4 2002/01/23 07:52:36 lampret`
`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`	`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`
`//`	`//`
`// Revision 1.3 2002/01/19 09:27:49 lampret`	`// Revision 1.3 2002/01/19 09:27:49 lampret`
`// SR[TEE] should be zero after reset.`	`// SR[TEE] should be zero after reset.`
Line 203...	Line 206...

`//`	`//`
`// Generate SPR address from base address and offset`	`// Generate SPR address from base address and offset`
`// OR from debug unit address`	`// OR from debug unit address`
`//`	`//`
`assign spr_addr = du_access ? du_addr : addrbase + {16'h0000, addrofs};`	`assign spr_addr = du_access ? du_addr : addrbase \| {16'h0000, addrofs};`

`//`	`//`
`// SPR is written by debug unit or by l.mtspr`	`// SPR is written by debug unit or by l.mtspr`
`//`	`//`
`assign spr_dat_o = du_write ? du_dat_du : dat_i;`	`assign spr_dat_o = du_write ? du_dat_du : dat_i;`