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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/03/11 01:26:57 lampret
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// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
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//
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
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// Fixed combinational loops.
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//
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//
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// Revision 1.4 2002/01/23 07:52:36 lampret
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// Revision 1.4 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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| Line 97... |
Line 100... |
// Clk & Rst
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// Clk & Rst
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clk, rst,
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clk, rst,
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// Internal CPU interface
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// Internal CPU interface
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flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
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flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
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epcr, eear, esr, except_start, except_started,
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epcr, eear, esr, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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// From/to other RISC units
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// From/to other RISC units
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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spr_dat_pic, spr_dat_tt, spr_dat_pm,
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Line 136... |
input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [width-1:0] epcr; // EPCR0
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input [width-1:0] epcr; // EPCR0
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input [width-1:0] eear; // EEAR0
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input [width-1:0] eear; // EEAR0
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input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
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input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
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input except_start; // Start of exception
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input except_started; // Exception was started
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input except_started; // Exception was started
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output [width-1:0] to_wbmux; // For l.mfspr
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output [width-1:0] to_wbmux; // For l.mfspr
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output epcr_we; // EPCR0 write enable
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output epcr_we; // EPCR0 write enable
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output eear_we; // EEAR0 write enable
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output eear_we; // EEAR0 write enable
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output esr_we; // ESR0 write enable
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output esr_we; // ESR0 write enable
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Line 342... |
//
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//
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// MTSPR/MFSPR interface
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// MTSPR/MFSPR interface
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//
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//
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always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
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spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
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spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
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case (sprs_op) // synopsys full_case parallel_case
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case (sprs_op) // synopsys parallel_case
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`OR1200_ALUOP_MTSR : begin
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`OR1200_ALUOP_MTSR : begin
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write_spr = 1'b1;
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write_spr = 1'b1;
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read_spr = 1'b0;
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read_spr = 1'b0;
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to_wbmux = 32'b0;
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to_wbmux = 32'b0;
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end
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end
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`OR1200_ALUOP_MFSR : begin
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`OR1200_ALUOP_MFSR : begin
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casex (spr_addr[`OR1200_SPR_GROUP_BITS])
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casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
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`OR1200_SPR_GROUP_TT:
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`OR1200_SPR_GROUP_TT:
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to_wbmux = spr_dat_tt;
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to_wbmux = spr_dat_tt;
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`OR1200_SPR_GROUP_PIC:
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`OR1200_SPR_GROUP_PIC:
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to_wbmux = spr_dat_pic;
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to_wbmux = spr_dat_pic;
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`OR1200_SPR_GROUP_PM:
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`OR1200_SPR_GROUP_PM:
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