| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.6 2001/10/21 17:57:16 lampret
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// Revision 1.6 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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| Line 147... |
Line 150... |
wire dtlb_swe;
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wire dtlb_swe;
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wire dtlb_sre;
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wire dtlb_sre;
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wire [31:0] dtlb_dat_o;
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wire [31:0] dtlb_dat_o;
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wire dtlb_en;
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wire dtlb_en;
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wire dtlb_ci;
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wire dtlb_ci;
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wire dtlb_done;
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reg dtlb_done;
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wire fault;
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wire fault;
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wire miss;
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wire miss;
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reg dcpu_cyc_dlyd;
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reg dcpu_stb_dlyd;
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//
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//
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// Implemented bits inside match and translate registers
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// Implemented bits inside match and translate registers
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//
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//
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// dtlbwYmrX: vpn 31-10 v 0
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// dtlbwYmrX: vpn 31-10 v 0
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| Line 177... |
Line 178... |
assign dcdmmu_adr_o = dcpu_adr_i;
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assign dcdmmu_adr_o = dcpu_adr_i;
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assign dcpu_tag_o = dcdmmu_tag_i;
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assign dcpu_tag_o = dcdmmu_tag_i;
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assign dcdmmu_cyc_o = dcpu_cyc_i;
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assign dcdmmu_cyc_o = dcpu_cyc_i;
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assign dcdmmu_stb_o = dcpu_stb_i;
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assign dcdmmu_stb_o = dcpu_stb_i;
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assign dcpu_err_o = dcdmmu_err_i;
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assign dcpu_err_o = dcdmmu_err_i;
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assign dcdmmu_ci_o = !dcpu_adr_i[30];
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assign dcdmmu_ci_o = dcpu_adr_i[31];
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`else
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`else
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//
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//
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// DTLB SPR access
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// DTLB SPR access
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| Line 206... |
Line 207... |
// dcpu_err_o
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// dcpu_err_o
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//
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//
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assign dcpu_err_o = miss | fault | dcdmmu_err_i;
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assign dcpu_err_o = miss | fault | dcdmmu_err_i;
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//
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//
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// Delay WISHBONE control signals in case DC is disabled and DMMU is
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// Assert dtlb_done one clock cycle after new address and dtlb_en must be active.
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// enabled to prevent premature external BIU access.
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//
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//
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always @(posedge rst or posedge clk)
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always @(posedge clk or posedge rst)
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if (rst)
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dcpu_cyc_dlyd <= #1 1'b0;
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else
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dcpu_cyc_dlyd <= #1 ~(miss | fault) & dcpu_cyc_i;
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always @(posedge rst or posedge clk)
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if (rst)
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if (rst)
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dcpu_stb_dlyd <= #1 1'b0;
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dtlb_done <= #1 1'b0;
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else if (dtlb_en)
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dtlb_done <= #1 dcpu_cyc_i;
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else
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else
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dcpu_stb_dlyd <= #1 ~(miss | fault) & dcpu_stb_i;
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dtlb_done <= #1 1'b0;
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//
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//
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// Cut transfer if something goes wrong with translation. If DC is disabled,
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// Cut transfer if something goes wrong with translation. If DC is disabled,
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// use delayed signals.
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// use delayed signals.
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//
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//
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assign dcdmmu_cyc_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dcpu_cyc_dlyd : (miss | fault) ? 1'b0 : dcpu_cyc_i;
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assign dcdmmu_cyc_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_cyc_i : (miss | fault) ? 1'b0 : dcpu_cyc_i;
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assign dcdmmu_stb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dcpu_stb_dlyd : (miss | fault) ? 1'b0 : dcpu_stb_i;
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assign dcdmmu_stb_o = (!dc_en & dmmu_en) ? ~(miss | fault) & dtlb_done & dcpu_stb_i : (miss | fault) ? 1'b0 : dcpu_stb_i;
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//
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//
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// Cache Inhibit
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// Cache Inhibit
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//
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//
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assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : 1'b0;
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assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : dcpu_adr_i[31];
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//
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//
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// Physical address is either translated virtual address or
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// Physical address is either translated virtual address or
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// simply equal when DMMU is disabled
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// simply equal when DMMU is disabled
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//
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//
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| Line 246... |
Line 244... |
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
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assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
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//
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//
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// Page fault exception logic
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// Page fault exception logic
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//
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//
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assign fault = dtlb_en & dtlb_done &
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assign fault = dtlb_done &
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( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled
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( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled
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|| (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled
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|| (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled
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|| (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled
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|| (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled
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|| (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled
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|| (dcpu_we_i & supv & !dtlb_swe) ); // Store in supv mode not enabled
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//
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//
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// TLB Miss exception logic
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// TLB Miss exception logic
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//
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//
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assign miss = dtlb_en & dtlb_done & !dtlb_hit;
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assign miss = dtlb_done & !dtlb_hit;
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//
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//
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// DTLB Enable
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// DTLB Enable
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//
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//
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assign dtlb_en = dmmu_en & dcpu_cyc_i & dcpu_stb_i;
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assign dtlb_en = dmmu_en & dcpu_cyc_i & dcpu_stb_i;
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| Line 280... |
Line 278... |
.uwe(dtlb_uwe),
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.uwe(dtlb_uwe),
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.ure(dtlb_ure),
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.ure(dtlb_ure),
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.swe(dtlb_swe),
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.swe(dtlb_swe),
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.sre(dtlb_sre),
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.sre(dtlb_sre),
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.ci(dtlb_ci),
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.ci(dtlb_ci),
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.done(dtlb_done),
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// SPR access
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// SPR access
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.spr_cs(dtlb_spr_access),
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.spr_cs(dtlb_spr_access),
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.spr_write(spr_write),
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.spr_write(spr_write),
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.spr_addr(spr_addr),
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.spr_addr(spr_addr),
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