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[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 573 and 597

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Rev 573	Rev 597
Line 59...	Line 59...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.2 2002/01/15 06:12:22 lampret`
	`// Fixed module name when compiling with OR1200_XILINX_RAM32X1D`
	`//`
`// Revision 1.1 2002/01/03 08:16:15 lampret`	`// Revision 1.1 2002/01/03 08:16:15 lampret`
`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`	`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
`//`	`//`
`// Revision 1.10 2001/11/05 14:48:00 lampret`	`// Revision 1.10 2001/11/05 14:48:00 lampret`
`// Added missing endif`	`// Added missing endif`
Line 237...	Line 240...
`// Instantiation of FPGA memory:`	`// Instantiation of FPGA memory:`
`//`	`//`
`// Virtex/Spartan2`	`// Virtex/Spartan2`
`//`	`//`

	`reg [4:0] addr_a_r;`

	`always @(posedge clk_a or posedge rst_a)`
	`if (ce_a)`
	`addr_a_r <= #1 addr_a;`

`//`	`//`
`// Block 0`	`// Block 0`
`//`	`//`
`or1200_xcv_ram32x8d xcv_ram32x8d_0 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_0 (`
`.DPO(do_a[7:0]),`	`.DPO(do_a[7:0]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[7:0]),`	`.D(di_b[7:0]),`
`.DPRA(addr_a),`	`.DPRA(addr_a_r),`
`.WCLK(clk_b),`	`.WCLK(clk_b),`
`.WE(we_b)`	`.WE(we_b)`
`);`	`);`

`//`	`//`
Line 258...	Line 267...
`or1200_xcv_ram32x8d xcv_ram32x8d_1 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_1 (`
`.DPO(do_a[15:8]),`	`.DPO(do_a[15:8]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[15:8]),`	`.D(di_b[15:8]),`
`.DPRA(addr_a),`	`.DPRA(addr_a_r),`
`.WCLK(clk_b),`	`.WCLK(clk_b),`
`.WE(we_b)`	`.WE(we_b)`
`);`	`);`


Line 272...	Line 281...
`or1200_xcv_ram32x8d xcv_ram32x8d_2 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_2 (`
`.DPO(do_a[23:16]),`	`.DPO(do_a[23:16]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[23:16]),`	`.D(di_b[23:16]),`
`.DPRA(addr_a),`	`.DPRA(addr_a_r),`
`.WCLK(clk_b),`	`.WCLK(clk_b),`
`.WE(we_b)`	`.WE(we_b)`
`);`	`);`

`//`	`//`
Line 285...	Line 294...
`or1200_xcv_ram32x8d xcv_ram32x8d_3 (`	`or1200_xcv_ram32x8d xcv_ram32x8d_3 (`
`.DPO(do_a[31:24]),`	`.DPO(do_a[31:24]),`
`.SPO(),`	`.SPO(),`
`.A(addr_b),`	`.A(addr_b),`
`.D(di_b[31:24]),`	`.D(di_b[31:24]),`
`.DPRA(addr_a),`	`.DPRA(addr_a_r),`
`.WCLK(clk_b),`	`.WCLK(clk_b),`
`.WE(we_b)`	`.WE(we_b)`
`);`	`);`

`else	`else

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[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Diff between revs 573 and 597