| Line 61... |
Line 61... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.3 2003/04/07 01:19:07 lampret
|
|
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
|
|
//
|
// Revision 1.2 2002/10/17 20:04:40 lampret
|
// Revision 1.2 2002/10/17 20:04:40 lampret
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
|
//
|
//
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// Revision 1.1 2002/01/03 08:16:15 lampret
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
|
| Line 312... |
Line 315... |
defparam lpm_ram_dq_component.lpm_width = dw,
|
defparam lpm_ram_dq_component.lpm_width = dw,
|
lpm_ram_dq_component.lpm_widthad = aw,
|
lpm_ram_dq_component.lpm_widthad = aw,
|
lpm_ram_dq_component.lpm_indata = "REGISTERED",
|
lpm_ram_dq_component.lpm_indata = "REGISTERED",
|
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
|
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
|
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
|
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
|
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
|
lpm_ram_dq_component.lpm_hint = "USE_EAB=OFF";
|
// examplar attribute lpm_ram_dq_component NOOPT TRUE
|
// examplar attribute lpm_ram_dq_component NOOPT TRUE
|
|
|
`else
|
`else
|
|
|
//
|
//
|
