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[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Diff between revs 1184 and 1200

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Rev 1184	Rev 1200
Line 61...	Line 61...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.5 2003/08/19 16:41:23 simons`
	`// Scan signals mess fixed.`
	`//`
`// Revision 1.4 2003/08/11 13:32:19 simons`	`// Revision 1.4 2003/08/11 13:32:19 simons`
`// BIST interface added for Artisan memory instances.`	`// BIST interface added for Artisan memory instances.`
`//`	`//`
`// Revision 1.3 2003/04/07 01:19:07 lampret`	`// Revision 1.3 2003/04/07 01:19:07 lampret`
`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`	`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
Line 104...	Line 107...
`include "or1200_defines.v"	`include "or1200_defines.v"

`module or1200_spram_64x24(`	`module or1200_spram_64x24(`
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`	`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
`endif	`endif
`// Generic synchronous single-port RAM interface`	`// Generic synchronous single-port RAM interface`
`clk, rst, ce, we, oe, addr, di, do`	`clk, rst, ce, we, oe, addr, di, do`
`);`	`);`

Line 120...	Line 123...

`ifdef OR1200_BIST	`ifdef OR1200_BIST
`//`	`//`
`// RAM BIST`	`// RAM BIST`
`//`	`//`
`input scanb_rst,`	`input mbist_si_i;`
`scanb_si,`	input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`scanb_en,`	`output mbist_so_o;`
`scanb_clk;`
`output scanb_so;`
`endif	`endif

`//`	`//`
`// Generic synchronous single-port RAM interface`	`// Generic synchronous single-port RAM interface`
`//`	`//`
Line 149...	Line 150...
`ifdef OR1200_ARTISAN_SSP	`ifdef OR1200_ARTISAN_SSP
`else	`else
`ifdef OR1200_VIRTUALSILICON_SSP	`ifdef OR1200_VIRTUALSILICON_SSP
`else	`else
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`assign scanb_so = scanb_si;`	`assign mbist_so_o = mbist_si_i;`
`endif	`endif
`endif	`endif
`endif	`endif

`ifdef OR1200_ARTISAN_SSP	`ifdef OR1200_ARTISAN_SSP
Line 172...	Line 173...
`art_hssp_64x24 artisan_ssp(`	`art_hssp_64x24 artisan_ssp(`
`endif	`endif
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_si_i),`
`.scanb_si(scanb_si),`	`.mbist_so_o(mbist_so_o),`
`.scanb_so(scanb_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.CLK(clk),`	`.CLK(clk),`
`.CEN(~ce),`	`.CEN(~ce),`
`.WEN(~we),`	`.WEN(~we),`
`.A(addr),`	`.A(addr),`
Line 247...	Line 246...
`vs_hdsp_64x24 vs_ssp(`	`vs_hdsp_64x24 vs_ssp(`
`endif	`endif
`endif	`endif
`ifdef OR1200_BIST	`ifdef OR1200_BIST
`// RAM BIST`	`// RAM BIST`
`.scanb_rst(scanb_rst),`	`.mbist_si_i(mbist_si_i),`
`.scanb_si(scanb_si),`	`.mbist_so_o(mbist_so_o),`
`.scanb_so(scanb_so),`	`.mbist_ctrl_i(mbist_ctrl_i),`
`.scanb_en(scanb_en),`
`.scanb_clk(scanb_clk),`
`endif	`endif
`.CK(clk),`	`.CK(clk),`
`.ADR(addr),`	`.ADR(addr),`
`.DI(di),`	`.DI(di),`
`.WEN(~we),`	`.WEN(~we),`

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[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Diff between revs 1184 and 1200