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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.8 2002/08/28 01:44:25 lampret
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// Removed some commented RTL. Fixed SR/ESR flag bug.
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//
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// Revision 1.7 2002/03/29 15:16:56 lampret
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// Revision 1.7 2002/03/29 15:16:56 lampret
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// Some of the warnings fixed.
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// Some of the warnings fixed.
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//
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//
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// Revision 1.6 2002/03/11 01:26:57 lampret
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// Revision 1.6 2002/03/11 01:26:57 lampret
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// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
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// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
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Line 105... |
module or1200_sprs(
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module or1200_sprs(
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// Clk & Rst
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// Clk & Rst
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clk, rst,
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clk, rst,
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// Internal CPU interface
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// Internal CPU interface
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flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
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flagforw, flag_we, flag, cyforw, cy_we, carry,
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addrbase, addrofs, dat_i, alu_op, branch_op,
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epcr, eear, esr, except_started,
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epcr, eear, esr, except_started,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
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// From/to other RISC units
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// From/to other RISC units
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//
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//
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// Internal CPU interface
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// Internal CPU interface
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//
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//
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input clk; // Clock
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input clk; // Clock
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input rst; // Reset
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input rst; // Reset
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output flag; // SR[F]
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input flagforw; // From ALU
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input flagforw; // From ALU
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input flag_we; // From ALU
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input flag_we; // From ALU
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output flag; // SR[F]
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input cyforw; // From ALU
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input cy_we; // From ALU
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output carry; // SR[CY]
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input [width-1:0] addrbase; // SPR base address
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input [width-1:0] addrbase; // SPR base address
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input [15:0] addrofs; // SPR offset
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input [15:0] addrofs; // SPR offset
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input [width-1:0] dat_i; // SPR write data
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input [width-1:0] dat_i; // SPR write data
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
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input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
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//
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//
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//
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//
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// What to write into SR
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// What to write into SR
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//
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//
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assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr :
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assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
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flag_we ? {sr[`OR1200_SR_FO:`OR1200_SR_CY], flagforw, sr[`OR1200_SR_CE:`OR1200_SR_SM]} : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]};
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
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(write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
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sr[`OR1200_SR_FO:`OR1200_SR_OV];
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assign to_sr[`OR1200_SR_CY] =
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
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cy_we ? cyforw :
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(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
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sr[`OR1200_SR_CY];
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assign to_sr[`OR1200_SR_F] =
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
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flag_we ? flagforw :
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(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
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sr[`OR1200_SR_F];
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assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
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(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
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(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
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sr[`OR1200_SR_CE:`OR1200_SR_SM];
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//
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//
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// Selects for system SPRs
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// Selects for system SPRs
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//
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//
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
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assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
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assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
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//
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//
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// Write enables for system SPRs
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// Write enables for system SPRs
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//
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//
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assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we;
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assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
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assign pc_we = (write_spr && (npc_sel | ppc_sel));
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assign pc_we = (write_spr && (npc_sel | ppc_sel));
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assign epcr_we = (write_spr && epcr_sel);
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assign epcr_we = (write_spr && epcr_sel);
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assign eear_we = (write_spr && eear_sel);
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assign eear_we = (write_spr && eear_sel);
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assign esr_we = (write_spr && esr_sel);
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assign esr_we = (write_spr && esr_sel);
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Line 347... |
// Flag alias
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// Flag alias
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//
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//
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assign flag = sr[`OR1200_SR_F];
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assign flag = sr[`OR1200_SR_F];
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//
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//
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// Carry alias
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//
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assign carry = sr[`OR1200_SR_CY];
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//
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// Supervision register
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// Supervision register
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
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sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
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