| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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//
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// Revision 1.14 2001/11/30 18:59:17 simons
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// Revision 1.14 2001/11/30 18:59:17 simons
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// force_dslot_fetch does not work - allways zero.
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// force_dslot_fetch does not work - allways zero.
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| Line 94... |
Line 97... |
// Internal i/f
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// Internal i/f
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id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op,
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id_freeze, ex_freeze, wb_freeze, flushpipe, if_insn, ex_insn, branch_op,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, rf_addrw, rfwb_op,
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wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
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wb_insn, simm, branch_addrofs, lsu_addrofs, sel_a, sel_b, lsu_op,
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multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
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multicycle, spr_addrimm, wbforw_valid, sig_syscall, sig_trap,
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force_dslot_fetch, has_dslot, id_macrc_op, ex_macrc_op, rfe, except_illegal
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force_dslot_fetch, has_dslot, ex_void, id_macrc_op, ex_macrc_op, rfe, except_illegal
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 133... |
Line 136... |
input wbforw_valid;
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input wbforw_valid;
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output sig_syscall;
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output sig_syscall;
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output sig_trap;
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output sig_trap;
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output force_dslot_fetch;
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output force_dslot_fetch;
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output has_dslot;
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output has_dslot;
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output ex_void;
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output id_macrc_op;
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output id_macrc_op;
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output ex_macrc_op;
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output ex_macrc_op;
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output rfe;
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output rfe;
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output except_illegal;
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output except_illegal;
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| Line 165... |
Line 169... |
reg [15:0] spr_addrimm;
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reg [15:0] spr_addrimm;
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reg sig_syscall;
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reg sig_syscall;
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reg sig_trap;
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reg sig_trap;
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reg except_illegal;
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reg except_illegal;
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reg ex_macrc_op;
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reg ex_macrc_op;
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wire id_void;
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//
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//
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// Register file read addresses
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// Register file read addresses
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//
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//
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assign rf_addra = if_insn[20:16];
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assign rf_addra = if_insn[20:16];
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| Line 181... |
Line 186... |
// instructions
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// instructions
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//
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//
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// SIMON
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// SIMON
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// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
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// assign force_dslot_fetch = ((|pre_branch_op) & (|lsu_op));
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assign force_dslot_fetch = 1'b0;
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assign force_dslot_fetch = 1'b0;
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assign has_dslot = |branch_op & ((id_insn[31:26] != `OR1200_OR32_NOP) | !id_insn[0]);
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assign has_dslot = |branch_op & !id_void;
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assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[0];
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assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0];
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//
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//
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// Sign/Zero extension of immediates
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// Sign/Zero extension of immediates
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//
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//
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assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
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assign simm = (imm_signextend == 1'b1) ? {{16{id_insn[15]}}, id_insn[15:0]} : {{16'b0}, id_insn[15:0]};
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