| Line 20... |
Line 20... |
//// - Avant! Two-Port Sync RAM (*) ////
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//// - Avant! Two-Port Sync RAM (*) ////
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//// - Virage 2-port Sync RAM ////
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//// - Virage 2-port Sync RAM ////
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//// ////
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//// ////
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//// Supported FPGA RAMs are: ////
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//// Supported FPGA RAMs are: ////
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//// - Xilinx Virtex RAMB4_S16_S16 ////
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//// - Xilinx Virtex RAMB4_S16_S16 ////
|
|
//// - Altera LPM ////
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//// ////
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//// ////
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//// To Do: ////
|
//// To Do: ////
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//// - fix Avant! ////
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//// - fix Avant! ////
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//// - xilinx rams need external tri-state logic ////
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//// - xilinx rams need external tri-state logic ////
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//// - add additional RAMs (Altera, VS etc) ////
|
//// - add additional RAMs ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
|
//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
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| Line 59... |
Line 60... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
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//
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//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.6 2002/03/28 19:25:42 lampret
|
|
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
|
|
//
|
// Revision 1.5 2002/02/01 19:56:54 lampret
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// Revision 1.5 2002/02/01 19:56:54 lampret
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// Fixed combinational loops.
|
// Fixed combinational loops.
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//
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//
|
// Revision 1.4 2002/01/23 07:52:36 lampret
|
// Revision 1.4 2002/01/23 07:52:36 lampret
|
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
|
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
|
| Line 396... |
Line 400... |
.DOB()
|
.DOB()
|
);
|
);
|
|
|
`else
|
`else
|
|
|
|
`ifdef OR1200_ALTERA_LPM
|
|
|
|
//
|
|
// Instantiation of FPGA memory:
|
|
//
|
|
// Altera LPM
|
|
//
|
|
// Added By Jamil Khatib
|
|
//
|
|
altqpram altqpram_component (
|
|
.wraddress_a (addr_a),
|
|
.inclocken_a (ce_a),
|
|
.wraddress_b (addr_b),
|
|
.wren_a (we_a),
|
|
.inclocken_b (ce_b),
|
|
.wren_b (we_b),
|
|
.inaclr_a (rst_a),
|
|
.inaclr_b (rst_b),
|
|
.inclock_a (clk_a),
|
|
.inclock_b (clk_b),
|
|
.data_a (di_a),
|
|
.data_b (di_b),
|
|
.q_a (do_a),
|
|
.q_b (do_b)
|
|
);
|
|
|
|
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
|
|
altqpram_component.width_write_a = dw,
|
|
altqpram_component.widthad_write_a = aw,
|
|
altqpram_component.numwords_write_a = dw,
|
|
altqpram_component.width_read_a = dw,
|
|
altqpram_component.widthad_read_a = aw,
|
|
altqpram_component.numwords_read_a = dw,
|
|
altqpram_component.width_write_b = dw,
|
|
altqpram_component.widthad_write_b = aw,
|
|
altqpram_component.numwords_write_b = dw,
|
|
altqpram_component.width_read_b = dw,
|
|
altqpram_component.widthad_read_b = aw,
|
|
altqpram_component.numwords_read_b = dw,
|
|
altqpram_component.indata_reg_a = "INCLOCK_A",
|
|
altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
|
|
altqpram_component.outdata_reg_a = "INCLOCK_A",
|
|
altqpram_component.indata_reg_b = "INCLOCK_B",
|
|
altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
|
|
altqpram_component.outdata_reg_b = "INCLOCK_B",
|
|
altqpram_component.indata_aclr_a = "INACLR_A",
|
|
altqpram_component.wraddress_aclr_a = "INACLR_A",
|
|
altqpram_component.wrcontrol_aclr_a = "INACLR_A",
|
|
altqpram_component.outdata_aclr_a = "INACLR_A",
|
|
altqpram_component.indata_aclr_b = "NONE",
|
|
altqpram_component.wraddress_aclr_b = "NONE",
|
|
altqpram_component.wrcontrol_aclr_b = "NONE",
|
|
altqpram_component.outdata_aclr_b = "INACLR_B",
|
|
altqpram_component.lpm_hint = "USE_ESB=ON";
|
|
//examplar attribute altqpram_component NOOPT TRUE
|
|
|
|
`else
|
|
|
//
|
//
|
// Generic double-port synchronous RAM model
|
// Generic double-port synchronous RAM model
|
//
|
//
|
|
|
//
|
//
|
| Line 409... |
Line 471... |
reg [dw-1:0] do_reg; // RAM data output register
|
reg [dw-1:0] do_reg; // RAM data output register
|
|
|
//
|
//
|
// Data output drivers
|
// Data output drivers
|
//
|
//
|
assign do_a = (oe_a) ? do_reg : {dw{1'bz}};
|
assign do_a = (oe_a) ? do_reg : {dw{1'b0}};
|
|
|
//
|
//
|
// RAM read
|
// RAM read
|
//
|
//
|
always @(posedge clk_a)
|
always @(posedge clk_a)
|
| Line 425... |
Line 487... |
//
|
//
|
always @(posedge clk_b)
|
always @(posedge clk_b)
|
if (ce_b && we_b)
|
if (ce_b && we_b)
|
mem[addr_b] <= #1 di_b;
|
mem[addr_b] <= #1 di_b;
|
|
|
|
`endif // !OR1200_ALTERA_LPM
|
`endif // !OR1200_XILINX_RAMB4_S16_S16
|
`endif // !OR1200_XILINX_RAMB4_S16_S16
|
`endif // !OR1200_XILINX_RAM32X1D
|
`endif // !OR1200_XILINX_RAM32X1D
|
`endif // !OR1200_VIRTUALSILICON_SSP_T1
|
`endif // !OR1200_VIRTUALSILICON_SSP_T1
|
`endif // !OR1200_VIRTUALSILICON_SSP_T2
|
`endif // !OR1200_VIRTUALSILICON_SSP_T2
|
`endif // !OR1200_VIRAGE_STP
|
`endif // !OR1200_VIRAGE_STP
|
