| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/01/28 01:16:00 lampret
|
|
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
|
|
//
|
// Revision 1.3 2002/01/18 07:56:00 lampret
|
// Revision 1.3 2002/01/18 07:56:00 lampret
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
|
//
|
//
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Revision 1.2 2002/01/14 06:18:22 lampret
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
| Line 86... |
Line 89... |
//
|
//
|
|
|
module or1200_du(
|
module or1200_du(
|
// RISC Internal Interface
|
// RISC Internal Interface
|
clk, rst,
|
clk, rst,
|
dcpu_cyc_i, dcpu_stb_i, dcpu_we_i,
|
dcpu_cycstb_i, dcpu_we_i,
|
icpu_cyc_i, icpu_stb_i, ex_freeze, branch_op, ex_insn, du_dsr,
|
icpu_cycstb_i, ex_freeze, branch_op, ex_insn, du_dsr,
|
du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
|
du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
|
|
|
// External Debug Interface
|
// External Debug Interface
|
dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
|
dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
|
| Line 108... |
Line 111... |
//
|
//
|
// RISC Internal Interface
|
// RISC Internal Interface
|
//
|
//
|
input clk; // Clock
|
input clk; // Clock
|
input rst; // Reset
|
input rst; // Reset
|
input dcpu_cyc_i; // LSU status
|
input dcpu_cycstb_i; // LSU status
|
input dcpu_stb_i; // LSU status
|
|
input dcpu_we_i; // LSU status
|
input dcpu_we_i; // LSU status
|
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cyc_i; // IFETCH unit status
|
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
|
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_stb_i; // IFETCH unit status
|
|
input ex_freeze; // EX stage freeze
|
input ex_freeze; // EX stage freeze
|
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
|
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
|
input [dw-1:0] ex_insn; // EX insn
|
input [dw-1:0] ex_insn; // EX insn
|
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
|
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
|
output du_stall; // Debug Unit Stall
|
output du_stall; // Debug Unit Stall
|
| Line 148... |
Line 149... |
|
|
|
|
//
|
//
|
// Some connections go directly from the CPU through DU to Debug I/F
|
// Some connections go directly from the CPU through DU to Debug I/F
|
//
|
//
|
assign dbg_lss_o = dcpu_cyc_i & dcpu_stb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
|
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
|
assign dbg_is_o = {1'b0, icpu_cyc_i & icpu_stb_i};
|
assign dbg_is_o = {1'b0, icpu_cycstb_i};
|
assign dbg_wp_o = 11'b000_0000_0000;
|
assign dbg_wp_o = 11'b000_0000_0000;
|
assign dbg_dat_o = du_dat_i;
|
assign dbg_dat_o = du_dat_i;
|
|
|
//
|
//
|
// Some connections go directly from Debug I/F through DU to the CPU
|
// Some connections go directly from Debug I/F through DU to the CPU
|
