| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/03/14 00:30:24 lampret
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// Added alternative for critical path in DU.
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//
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Revision 1.5 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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//
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Revision 1.4 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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| Line 92... |
Line 95... |
//
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//
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|
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module or1200_du(
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module or1200_du(
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// RISC Internal Interface
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// RISC Internal Interface
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clk, rst,
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clk, rst,
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dcpu_cycstb_i, dcpu_we_i,
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dcpu_cycstb_i, dcpu_we_i, icpu_cycstb_i,
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icpu_cycstb_i, ex_freeze, branch_op, ex_insn, du_dsr,
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ex_freeze, branch_op, ex_insn,
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du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
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spr_dat_npc, rf_dataw,
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du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
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du_read, du_write, du_except,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
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|
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// External Debug Interface
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// External Debug Interface
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
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| Line 120... |
Line 125... |
input dcpu_we_i; // LSU status
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input dcpu_we_i; // LSU status
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input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
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input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
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input ex_freeze; // EX stage freeze
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input ex_freeze; // EX stage freeze
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
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input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
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input [dw-1:0] ex_insn; // EX insn
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input [dw-1:0] ex_insn; // EX insn
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input [31:0] spr_dat_npc; // Next PC (for trace)
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input [31:0] rf_dataw; // ALU result (for trace)
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output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
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output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
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output du_stall; // Debug Unit Stall
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output du_stall; // Debug Unit Stall
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output [aw-1:0] du_addr; // Debug Unit Address
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output [aw-1:0] du_addr; // Debug Unit Address
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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input [dw-1:0] du_dat_i; // Debug Unit Data In
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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output [dw-1:0] du_dat_o; // Debug Unit Data Out
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| Line 154... |
Line 161... |
//
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//
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// Some connections go directly from the CPU through DU to Debug I/F
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// Some connections go directly from the CPU through DU to Debug I/F
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//
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//
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`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
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`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
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assign dbg_lss_o = 4'b0000;
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assign dbg_lss_o = 4'b0000;
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reg [1:0] dbg_is_o;
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//
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// Show insn activity (temp, must be removed)
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//
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always @(posedge clk or posedge rst)
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if (rst)
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dbg_is_o <= #1 2'b00;
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else if (!ex_freeze &
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~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
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dbg_is_o <= #1 ~dbg_is_o;
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`ifdef UNUSED
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assign dbg_is_o = 2'b00;
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assign dbg_is_o = 2'b00;
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`endif
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`else
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`else
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assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
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assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
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assign dbg_is_o = {1'b0, icpu_cycstb_i};
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assign dbg_is_o = {1'b0, icpu_cycstb_i};
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`endif
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`endif
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assign dbg_wp_o = 11'b000_0000_0000;
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assign dbg_wp_o = 11'b000_0000_0000;
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| Line 218... |
Line 238... |
reg dbg_bp_r;
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reg dbg_bp_r;
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`ifdef OR1200_DU_READREGS
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`ifdef OR1200_DU_READREGS
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reg [31:0] spr_dat_o;
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reg [31:0] spr_dat_o;
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`endif
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`endif
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reg [13:0] except_stop; // Exceptions that stop because of DSR
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reg [13:0] except_stop; // Exceptions that stop because of DSR
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`ifdef OR1200_DU_TB_IMPLEMENTED
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wire tb_enw;
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reg [7:0] tb_wadr;
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reg [31:0] tb_timstmp;
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`endif
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wire [31:0] tbia_dat_o;
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wire [31:0] tbim_dat_o;
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wire [31:0] tbar_dat_o;
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wire [31:0] tbts_dat_o;
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//
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//
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// DU registers address decoder
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// DU registers address decoder
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//
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//
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`ifdef OR1200_DU_DMR1
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`ifdef OR1200_DU_DMR1
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assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
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assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DMR1));
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`endif
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`endif
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`ifdef OR1200_DU_DSR
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`ifdef OR1200_DU_DSR
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assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
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assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DSR));
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`endif
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`endif
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`ifdef OR1200_DU_DRR
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`ifdef OR1200_DU_DRR
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assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
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assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_OFS_DRR));
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`endif
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`endif
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//
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//
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// Decode started exception
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// Decode started exception
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//
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//
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| Line 351... |
Line 380... |
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//
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//
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// Read DU registers
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// Read DU registers
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//
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//
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`ifdef OR1200_DU_READREGS
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`ifdef OR1200_DU_READREGS
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always @(spr_addr or dsr or drr or dmr1 or dmr2)
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always @(spr_addr or dsr or drr or dmr1 or dmr2 or
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case (spr_addr[`OR1200_SPR_OFS_BITS])
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tbia_dat_o or tbim_dat_o or tbar_dat_o or tb_wadr)
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casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
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`ifdef OR1200_DU_DMR1
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`ifdef OR1200_DU_DMR1
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`OR1200_DU_OFS_DMR1:
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`OR1200_DU_OFS_DMR1:
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spr_dat_o = {8'b0, dmr1, 22'b0};
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spr_dat_o = {8'b0, dmr1, 22'b0};
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`endif
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`endif
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`ifdef OR1200_DU_DMR2
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`ifdef OR1200_DU_DMR2
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| Line 369... |
Line 399... |
`endif
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`endif
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`ifdef OR1200_DU_DRR
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`ifdef OR1200_DU_DRR
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`OR1200_DU_OFS_DRR:
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`OR1200_DU_OFS_DRR:
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spr_dat_o = {18'b0, drr};
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spr_dat_o = {18'b0, drr};
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`endif
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`endif
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`ifdef OR1200_DU_TB_IMPLEMENTED
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`OR1200_DU_OFS_TBADR:
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spr_dat_o = {24'h000000, tb_wadr};
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`OR1200_DU_OFS_TBIA:
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spr_dat_o = tbia_dat_o;
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`OR1200_DU_OFS_TBIM:
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spr_dat_o = tbim_dat_o;
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`OR1200_DU_OFS_TBAR:
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spr_dat_o = tbar_dat_o;
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`OR1200_DU_OFS_TBTS:
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spr_dat_o = tbts_dat_o;
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`endif
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default:
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default:
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spr_dat_o = 32'h0000_0000;
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spr_dat_o = 32'h0000_0000;
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endcase
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endcase
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`endif
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`endif
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//
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//
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// DSR alias
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// DSR alias
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//
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//
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assign du_dsr = dsr;
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assign du_dsr = dsr;
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`ifdef OR1200_DU_TB_IMPLEMENTED
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//
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// Simple trace buffer
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// (right now hardcoded for Xilinx Virtex FPGAs)
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//
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// Stores last 256 instruction addresses, instruction
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// machine words and ALU results
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//
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//
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// Trace buffer write enable
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//
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assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
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//
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// Trace buffer write address pointer
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//
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always @(posedge clk or posedge rst)
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if (rst)
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tb_wadr <= #1 8'h00;
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else if (tb_enw)
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tb_wadr <= #1 tb_wadr + 8'd1;
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//
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// Free running counter (time stamp)
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//
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always @(posedge clk or posedge rst)
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if (rst)
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tb_timstmp <= #1 32'h00000000;
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else if (!dbg_bp_r)
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tb_timstmp <= #1 tb_timstmp + 32'd1;
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//
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// Trace buffer RAMs
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//
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RAMB4_S16_S16 tbia_ramb4_s16_0(
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.CLKA(clk),
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.RSTA(rst),
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.ADDRA(tb_wadr),
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.DIA(spr_dat_npc[15:0]),
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.ENA(1'b1),
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.WEA(tb_enw),
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.DOA(),
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.CLKB(clk),
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.RSTB(rst),
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.ADDRB(spr_addr[7:0]),
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.DIB(16'h0000),
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.ENB(1'b1),
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.WEB(1'b0),
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.DOB(tbia_dat_o[15:0])
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);
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RAMB4_S16_S16 tbia_ramb4_s16_1(
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.CLKA(clk),
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.RSTA(rst),
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.ADDRA(tb_wadr),
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.DIA(spr_dat_npc[31:16]),
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.ENA(1'b1),
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.WEA(tb_enw),
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.DOA(),
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.CLKB(clk),
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.RSTB(rst),
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.ADDRB(spr_addr[7:0]),
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.DIB(16'h0000),
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.ENB(1'b1),
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.WEB(1'b0),
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.DOB(tbia_dat_o[31:16])
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);
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RAMB4_S16_S16 tbim_ramb4_s16_0(
|
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.CLKA(clk),
|
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.RSTA(rst),
|
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.ADDRA(tb_wadr),
|
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.DIA(ex_insn[15:0]),
|
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.ENA(1'b1),
|
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.WEA(tb_enw),
|
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.DOA(),
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|
|
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.CLKB(clk),
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.RSTB(rst),
|
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.ADDRB(spr_addr[7:0]),
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.DIB(16'h0000),
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.ENB(1'b1),
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.WEB(1'b0),
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.DOB(tbim_dat_o[15:0])
|
|
);
|
|
|
|
RAMB4_S16_S16 tbim_ramb4_s16_1(
|
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.CLKA(clk),
|
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.RSTA(rst),
|
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.ADDRA(tb_wadr),
|
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.DIA(ex_insn[31:16]),
|
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.ENA(1'b1),
|
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.WEA(tb_enw),
|
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.DOA(),
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|
|
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.CLKB(clk),
|
|
.RSTB(rst),
|
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.ADDRB(spr_addr[7:0]),
|
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.DIB(16'h0000),
|
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.ENB(1'b1),
|
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.WEB(1'b0),
|
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.DOB(tbim_dat_o[31:16])
|
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);
|
|
|
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RAMB4_S16_S16 tbar_ramb4_s16_0(
|
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.CLKA(clk),
|
|
.RSTA(rst),
|
|
.ADDRA(tb_wadr),
|
|
.DIA(rf_dataw[15:0]),
|
|
.ENA(1'b1),
|
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.WEA(tb_enw),
|
|
.DOA(),
|
|
|
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.CLKB(clk),
|
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.RSTB(rst),
|
|
.ADDRB(spr_addr[7:0]),
|
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.DIB(16'h0000),
|
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.ENB(1'b1),
|
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.WEB(1'b0),
|
|
.DOB(tbar_dat_o[15:0])
|
|
);
|
|
|
|
RAMB4_S16_S16 tbar_ramb4_s16_1(
|
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.CLKA(clk),
|
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.RSTA(rst),
|
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.ADDRA(tb_wadr),
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.DIA(rf_dataw[31:16]),
|
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.ENA(1'b1),
|
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.WEA(tb_enw),
|
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.DOA(),
|
|
|
|
.CLKB(clk),
|
|
.RSTB(rst),
|
|
.ADDRB(spr_addr[7:0]),
|
|
.DIB(16'h0000),
|
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.ENB(1'b1),
|
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.WEB(1'b0),
|
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.DOB(tbar_dat_o[31:16])
|
|
);
|
|
|
|
RAMB4_S16_S16 tbts_ramb4_s16_0(
|
|
.CLKA(clk),
|
|
.RSTA(rst),
|
|
.ADDRA(tb_wadr),
|
|
.DIA(tb_timstmp[15:0]),
|
|
.ENA(1'b1),
|
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.WEA(tb_enw),
|
|
.DOA(),
|
|
|
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.CLKB(clk),
|
|
.RSTB(rst),
|
|
.ADDRB(spr_addr[7:0]),
|
|
.DIB(16'h0000),
|
|
.ENB(1'b1),
|
|
.WEB(1'b0),
|
|
.DOB(tbts_dat_o[15:0])
|
|
);
|
|
|
|
RAMB4_S16_S16 tbts_ramb4_s16_1(
|
|
.CLKA(clk),
|
|
.RSTA(rst),
|
|
.ADDRA(tb_wadr),
|
|
.DIA(tb_timstmp[31:16]),
|
|
.ENA(1'b1),
|
|
.WEA(tb_enw),
|
|
.DOA(),
|
|
|
|
.CLKB(clk),
|
|
.RSTB(rst),
|
|
.ADDRB(spr_addr[7:0]),
|
|
.DIB(16'h0000),
|
|
.ENB(1'b1),
|
|
.WEB(1'b0),
|
|
.DOB(tbts_dat_o[31:16])
|
|
);
|
|
|
`else
|
`else
|
|
assign tbia_dat_o = 32'h0000_0000;
|
|
assign tbim_dat_o = 32'h0000_0000;
|
|
assign tbar_dat_o = 32'h0000_0000;
|
|
assign tbts_dat_o = 32'h0000_0000;
|
|
|
|
`endif // OR1200_DU_TB_IMPLEMENTED
|
|
|
|
`else // OR1200_DU_IMPLEMENTED
|
|
|
//
|
//
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
// When DU is not implemented, drive all outputs as would when DU is disabled
|
//
|
//
|
assign dbg_bp_o = 1'b0;
|
assign dbg_bp_o = 1'b0;
|
