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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.12 2002/08/22 02:16:45 lampret
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// Fixed IMMU bug.
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//
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// Revision 1.11 2002/08/18 19:54:28 lampret
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// Revision 1.11 2002/08/18 19:54:28 lampret
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// Added store buffer.
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// Added store buffer.
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//
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//
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Revision 1.10 2002/07/14 22:17:17 lampret
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
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| Line 141... |
Line 144... |
sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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except_started, except_stop, ex_void,
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except_started, except_stop, ex_void,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
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esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
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);
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);
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//
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//
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// I/O
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// I/O
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//
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//
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| Line 179... |
Line 182... |
input esr_we;
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input esr_we;
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input pc_we;
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input pc_we;
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output [31:0] epcr;
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output [31:0] epcr;
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output [31:0] eear;
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output [31:0] eear;
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output [`OR1200_SR_WIDTH-1:0] esr;
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output [`OR1200_SR_WIDTH-1:0] esr;
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input [`OR1200_SR_WIDTH-1:0] to_sr;
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input sr_we;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [31:0] lsu_addr;
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input [31:0] lsu_addr;
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output flushpipe;
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output flushpipe;
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output extend_flush;
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output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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| Line 229... |
Line 234... |
//
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//
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assign except_started = extend_flush & except_start;
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assign except_started = extend_flush & except_start;
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assign lr_sav = ex_pc[31:2];
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assign lr_sav = ex_pc[31:2];
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux. except_test fails
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux, except_tets almost works (priority fails)
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
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assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
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//
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//
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// Order defines exception detection priority
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// Order defines exception detection priority
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| Line 347... |
Line 349... |
ex_exceptflags <= #1 3'b000;
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ex_exceptflags <= #1 3'b000;
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delayed1_ex_dslot <= #1 ex_dslot;
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delayed1_ex_dslot <= #1 ex_dslot;
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delayed2_ex_dslot <= #1 delayed1_ex_dslot;
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delayed2_ex_dslot <= #1 delayed1_ex_dslot;
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end
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end
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else if (!ex_freeze) begin
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else if (!ex_freeze) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display("%t: ex_pc <= %h", $time, id_pc);
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// synopsys translate_on
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`endif
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ex_dslot <= #1 branch_taken;
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ex_dslot <= #1 branch_taken;
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ex_pc <= #1 id_pc;
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ex_pc <= #1 id_pc;
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ex_exceptflags <= #1 id_exceptflags;
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ex_exceptflags <= #1 id_exceptflags;
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delayed1_ex_dslot <= #1 ex_dslot;
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delayed1_ex_dslot <= #1 ex_dslot;
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delayed2_ex_dslot <= #1 delayed1_ex_dslot;
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delayed2_ex_dslot <= #1 delayed1_ex_dslot;
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| Line 406... |
Line 403... |
case (state) // synopsys full_case parallel_case
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case (state) // synopsys full_case parallel_case
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`OR1200_EXCEPTFSM_IDLE:
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`OR1200_EXCEPTFSM_IDLE:
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if (except_flushpipe) begin
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if (except_flushpipe) begin
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state <= #1 `OR1200_EXCEPTFSM_FLU1;
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state <= #1 `OR1200_EXCEPTFSM_FLU1;
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extend_flush <= #1 1'b1;
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extend_flush <= #1 1'b1;
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if (ex_dslot) begin
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esr <= #1 sr_we ? to_sr : sr;
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display(" INFO: Exception during first delay slot instruction.");
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// synopsys translate_on
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`endif
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end
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else if (delayed1_ex_dslot) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display(" INFO: Exception during second (NOP) delay slot instruction.");
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// synopsys translate_on
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`endif
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end
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else if (delayed2_ex_dslot) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
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// synopsys translate_on
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`endif
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end
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else begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display(" INFO: Exception during normal (no delay slot) instruction.");
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// synopsys translate_on
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`endif
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end
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esr <= #1 sr;
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casex (except_trig)
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casex (except_trig)
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13'b1_xxxx_xxxx_xxxx: begin
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13'b1_xxxx_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_TICK;
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except_type <= #1 `OR1200_EXCEPT_TICK;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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Line 493... |
if (esr_we)
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if (esr_we)
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esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
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esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
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end
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end
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`OR1200_EXCEPTFSM_FLU1:
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`OR1200_EXCEPTFSM_FLU1:
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if (icpu_ack_i | icpu_err_i | genpc_freeze)
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if (icpu_ack_i | icpu_err_i | genpc_freeze)
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// if (!if_stall | genpc_freeze)
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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state <= #1 `OR1200_EXCEPTFSM_FLU2;
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`OR1200_EXCEPTFSM_FLU2:
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`OR1200_EXCEPTFSM_FLU2:
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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if (except_type == `OR1200_EXCEPT_TRAP) begin
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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extend_flush <= #1 1'b0;
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extend_flush <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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end
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end
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else
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else
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// if (!if_stall & !id_freeze)
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state <= #1 `OR1200_EXCEPTFSM_FLU3;
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state <= #1 `OR1200_EXCEPTFSM_FLU3;
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`OR1200_EXCEPTFSM_FLU3:
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`OR1200_EXCEPTFSM_FLU3:
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// if (!if_stall && !id_freeze)
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begin
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begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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if (except_flushpipe)
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$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);
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// synopsys translate_on
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`endif
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state <= #1 `OR1200_EXCEPTFSM_FLU4;
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state <= #1 `OR1200_EXCEPTFSM_FLU4;
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end
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end
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`OR1200_EXCEPTFSM_FLU4: begin
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`OR1200_EXCEPTFSM_FLU4: begin
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state <= #1 `OR1200_EXCEPTFSM_FLU5;
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state <= #1 `OR1200_EXCEPTFSM_FLU5;
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extend_flush <= #1 1'b0;
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extend_flush <= #1 1'b0;
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extend_flush_last <= #1 1'b0; // damjan
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extend_flush_last <= #1 1'b0; // damjan
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end
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end
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`OR1200_EXCEPTFSM_FLU5: begin
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`OR1200_EXCEPTFSM_FLU5: begin
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if (!if_stall && !id_freeze) begin
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if (!if_stall && !id_freeze) begin
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`ifdef OR1200_VERBOSE
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// synopsys translate_off
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$display(" INFO: Just finished flushing pipeline.");
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// synopsys translate_on
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`endif
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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extend_flush_last <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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end
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end
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end
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end
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