| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
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// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2002/01/14 21:11:50 lampret
|
|
// Changed alignment exception EPCR. Not tested yet.
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|
//
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Fixed order of syscall and range exceptions.
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// Fixed order of syscall and range exceptions.
|
//
|
//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
|
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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| Line 112... |
Line 115... |
// Clock and reset
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// Clock and reset
|
clk, rst,
|
clk, rst,
|
|
|
// Internal i/f
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// Internal i/f
|
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
|
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
|
sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
|
branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
|
branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
|
if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
|
if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
|
except_started, except_stop,
|
except_started, except_stop, has_dslot,
|
wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
|
spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
|
esr, sr, lsu_addr
|
esr, sr, lsu_addr
|
);
|
);
|
|
|
//
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//
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// I/O
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// I/O
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| Line 132... |
Line 135... |
input sig_illegal;
|
input sig_illegal;
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input sig_align;
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input sig_align;
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input sig_range;
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input sig_range;
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input sig_dtlbmiss;
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input sig_dtlbmiss;
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input sig_dmmufault;
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input sig_dmmufault;
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input sig_inthigh;
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input sig_int;
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input sig_syscall;
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input sig_syscall;
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input sig_trap;
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input sig_trap;
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input sig_itlbmiss;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_immufault;
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input sig_intlow;
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input sig_tick;
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input branch_taken;
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input branch_taken;
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input id_freeze;
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input id_freeze;
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input ex_freeze;
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input ex_freeze;
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input wb_freeze;
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input wb_freeze;
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input if_stall;
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input if_stall;
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| Line 162... |
Line 165... |
output extend_flush;
|
output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output except_start;
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output except_start;
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output except_started;
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output except_started;
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output [12:0] except_stop;
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output [12:0] except_stop;
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output [31:0] wb_pc;
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input has_dslot;
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output [31:0] ex_pc;
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output [31:0] spr_dat_ppc;
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output [31:0] id_pc;
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output [31:0] spr_dat_npc;
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|
|
//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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| Line 176... |
Line 179... |
reg [31:0] ex_pc;
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reg [31:0] ex_pc;
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reg [31:0] wb_pc;
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reg [31:0] wb_pc;
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reg [31:0] epcr;
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reg [31:0] epcr;
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reg [31:0] eear;
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reg [31:0] eear;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [3:0] id_exceptflags;
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reg [2:0] id_exceptflags;
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reg [3:0] ex_exceptflags;
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reg [2:0] ex_exceptflags;
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reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
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reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
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reg extend_flush;
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reg extend_flush;
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reg extend_flush_last;
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reg extend_flush_last;
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reg ex_dslot;
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reg ex_dslot;
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reg delayed1_ex_dslot;
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reg delayed1_ex_dslot;
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reg delayed2_ex_dslot;
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reg delayed2_ex_dslot;
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wire except_started;
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wire except_started;
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wire [12:0] except_trig;
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wire [12:0] except_trig;
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wire except_flushpipe;
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wire except_flushpipe;
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reg [2:0] delayed_eir;
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reg [2:0] delayed_iee;
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wire inthigh_pending;
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reg [2:0] delayed_tee;
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wire intlow_pending;
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wire int_pending;
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wire tick_pending;
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|
|
//
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//
|
// Simple combinatorial logic
|
// Simple combinatorial logic
|
//
|
//
|
assign except_started = extend_flush & except_start;
|
assign except_started = extend_flush & except_start;
|
assign lr_sav = ex_pc[31:2];
|
assign lr_sav = ex_pc[31:2];
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|
assign spr_dat_ppc = wb_pc;
|
|
assign spr_dat_npc = has_dslot ? ex_pc : id_pc;
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
|
//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
|
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
|
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
|
assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
|
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
|
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
|
|
|
//
|
//
|
// Order defines exception detection priority
|
// Order defines exception detection priority
|
//
|
//
|
assign except_trig = {
|
assign except_trig = {
|
inthigh_pending & ~du_dsr[`OR1200_DU_DSR_HPINTE],
|
int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
|
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[3] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
|
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
|
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
|
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
|
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
|
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
|
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
|
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
|
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
|
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
assign except_stop = {
|
assign except_stop = {
|
inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
|
int_pending & du_dsr[`OR1200_DU_DSR_IE],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[3] & du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
|
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
|
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_align & du_dsr[`OR1200_DU_DSR_AE],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
|
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
|
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
|
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
|
sig_range & du_dsr[`OR1200_DU_DSR_RE],
|
sig_range & du_dsr[`OR1200_DU_DSR_RE],
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
|
};
|
};
|
|
|
| Line 241... |
Line 247... |
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
id_pc <= #1 32'd0;
|
id_pc <= #1 32'd0;
|
id_exceptflags <= #1 4'b0000;
|
id_exceptflags <= #1 3'b000;
|
end
|
end
|
else if (flushpipe) begin
|
else if (flushpipe) begin
|
id_pc <= #1 32'h0000_0000;
|
id_pc <= #1 32'h0000_0000;
|
id_exceptflags <= #1 4'b0000;
|
id_exceptflags <= #1 3'b000;
|
end
|
end
|
else if (!id_freeze) begin
|
else if (!id_freeze) begin
|
id_pc <= #1 if_pc;
|
id_pc <= #1 if_pc;
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
|
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
|
end
|
end
|
end
|
end
|
|
|
//
|
//
|
// delayed_eir
|
// delayed_iee
|
|
//
|
|
// SR[IEE] should not enable interrupts right away
|
|
// when it is restored with l.rfe. Instead delayed_iee
|
|
// together with SR[IEE] enables interrupts once
|
|
// pipeline is again ready.
|
|
//
|
|
always @(posedge rst or posedge clk)
|
|
if (rst)
|
|
delayed_iee <= #1 3'b000;
|
|
else if (!sr[`OR1200_SR_IEE])
|
|
delayed_iee <= #1 3'b000;
|
|
else
|
|
delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
|
|
|
|
//
|
|
// delayed_tee
|
//
|
//
|
// SR[EIR] should not enable interrupts right away
|
// SR[TEE] should not enable tick exceptions right away
|
// when it is restored with l.rfe. Instead delayed_eir
|
// when it is restored with l.rfe. Instead delayed_tee
|
// together with SR[EIR] enables interrupts once
|
// together with SR[TEE] enables tick exceptions once
|
// pipeline is again ready.
|
// pipeline is again ready.
|
//
|
//
|
always @(posedge rst or posedge clk)
|
always @(posedge rst or posedge clk)
|
if (rst)
|
if (rst)
|
delayed_eir <= #1 3'b000;
|
delayed_tee <= #1 3'b000;
|
else if (!sr[`OR1200_SR_EIR])
|
else if (!sr[`OR1200_SR_TEE])
|
delayed_eir <= #1 3'b000;
|
delayed_tee <= #1 3'b000;
|
else
|
else
|
delayed_eir <= #1 {delayed_eir[1:0], 1'b1};
|
delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
|
|
|
//
|
//
|
// PC and Exception flags pipelines
|
// PC and Exception flags pipelines
|
//
|
//
|
always @(posedge clk or posedge rst) begin
|
always @(posedge clk or posedge rst) begin
|
if (rst) begin
|
if (rst) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'd0;
|
ex_pc <= #1 32'd0;
|
ex_exceptflags <= #1 4'b0000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (flushpipe) begin
|
else if (flushpipe) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 32'h0000_0000;
|
ex_pc <= #1 32'h0000_0000;
|
ex_exceptflags <= #1 4'b0000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed1_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
delayed2_ex_dslot <= #1 1'b0;
|
end
|
end
|
else if (!ex_freeze & id_freeze) begin
|
else if (!ex_freeze & id_freeze) begin
|
ex_dslot <= #1 1'b0;
|
ex_dslot <= #1 1'b0;
|
ex_pc <= #1 id_pc;
|
ex_pc <= #1 id_pc;
|
ex_exceptflags <= #1 4'b0000;
|
ex_exceptflags <= #1 3'b000;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed1_ex_dslot <= #1 ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
end
|
end
|
else if (!ex_freeze) begin
|
else if (!ex_freeze) begin
|
`ifdef OR1200_VERBOSE
|
`ifdef OR1200_VERBOSE
|
| Line 345... |
Line 367... |
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
extend_flush <= #1 1'b0;
|
extend_flush <= #1 1'b0;
|
epcr <= #1 32'b0;
|
epcr <= #1 32'b0;
|
eear <= #1 32'b0;
|
eear <= #1 32'b0;
|
esr <= #1 `OR1200_SR_WIDTH'b010;
|
esr <= #1 `OR1200_SR_WIDTH'b001;
|
extend_flush_last <= #1 1'b0;
|
extend_flush_last <= #1 1'b0;
|
end
|
end
|
else begin
|
else begin
|
case (state) // synopsys full_case parallel_case
|
case (state) // synopsys full_case parallel_case
|
`OR1200_EXCEPTFSM_IDLE:
|
`OR1200_EXCEPTFSM_IDLE:
|
| Line 386... |
Line 408... |
end
|
end
|
|
|
esr <= #1 sr;
|
esr <= #1 sr;
|
casex (except_trig)
|
casex (except_trig)
|
13'b1_xxxx_xxxx_xxxx: begin
|
13'b1_xxxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_HPINT;
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_1xxx_xxxx_xxxx: begin
|
13'b0_1xxx_xxxx_xxxx: begin
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| Line 429... |
Line 451... |
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
eear <= #1 lsu_addr;
|
eear <= #1 lsu_addr;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
end
|
end
|
13'b0_0000_0000_1xxx: begin
|
13'b0_0000_0000_1xxx: begin
|
except_type <= #1 `OR1200_EXCEPT_LPINT;
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
end
|
end
|
13'b0_0000_0000_01xx: begin
|
13'b0_0000_0000_01xx: begin
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| Line 458... |
Line 480... |
if (epcr_we)
|
if (epcr_we)
|
epcr <= #1 datain;
|
epcr <= #1 datain;
|
if (eear_we)
|
if (eear_we)
|
eear <= #1 datain;
|
eear <= #1 datain;
|
if (esr_we)
|
if (esr_we)
|
esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
|
esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
|
end
|
end
|
`OR1200_EXCEPTFSM_FLU1:
|
`OR1200_EXCEPTFSM_FLU1:
|
// if (!if_stall & !id_freeze)
|
// if (!if_stall & !id_freeze)
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
`OR1200_EXCEPTFSM_FLU2:
|
`OR1200_EXCEPTFSM_FLU2:
|
