| Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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//
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Changed alignment exception EPCR. Not tested yet.
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// Changed alignment exception EPCR. Not tested yet.
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| Line 208... |
Line 211... |
assign spr_dat_ppc = wb_pc;
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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//
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//
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// Order defines exception detection priority
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// Order defines exception detection priority
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//
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//
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assign except_trig = {
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assign except_trig = {
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| Line 370... |
Line 374... |
state <= #1 `OR1200_EXCEPTFSM_IDLE;
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state <= #1 `OR1200_EXCEPTFSM_IDLE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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except_type <= #1 `OR1200_EXCEPT_NONE;
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extend_flush <= #1 1'b0;
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extend_flush <= #1 1'b0;
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epcr <= #1 32'b0;
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epcr <= #1 32'b0;
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eear <= #1 32'b0;
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eear <= #1 32'b0;
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esr <= #1 `OR1200_SR_WIDTH'b001;
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esr <= #1 {1'b1, {`OR1200_SR_WIDTH-3{1'b0}}, 2'b11};
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extend_flush_last <= #1 1'b0;
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extend_flush_last <= #1 1'b0;
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end
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end
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else begin
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else begin
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case (state) // synopsys full_case parallel_case
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case (state) // synopsys full_case parallel_case
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`OR1200_EXCEPTFSM_IDLE:
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`OR1200_EXCEPTFSM_IDLE:
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| Line 431... |
Line 435... |
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_0001_xxxx_xxxx: begin
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13'b0_0001_xxxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_1xxx_xxxx: begin
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13'b0_0000_1xxx_xxxx: begin
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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except_type <= #1 `OR1200_EXCEPT_ALIGN;
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eear <= #1 lsu_addr;
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eear <= #1 lsu_addr;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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| Line 463... |
Line 468... |
except_type <= #1 `OR1200_EXCEPT_RANGE;
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except_type <= #1 `OR1200_EXCEPT_RANGE;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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13'b0_0000_0000_001x: begin
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13'b0_0000_0000_001x: begin
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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except_type <= #1 `OR1200_EXCEPT_TRAP;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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eear <= #1 32'h0000_0000;
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epcr <= #1 ex_dslot ? wb_pc : ex_pc;
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end
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end
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13'b0_0000_0000_0001: begin
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13'b0_0000_0000_0001: begin
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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except_type <= #1 `OR1200_EXCEPT_SYSCALL;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
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end
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end
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