OpenCores

Rev 617	Rev 660
Line 42...	Line 42...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// CVS Revision History`	`// CVS Revision History`
`//`	`//`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.8 2002/01/28 01:16:00 lampret`
	`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
	`//`
`// Revision 1.7 2002/01/23 07:52:36 lampret`	`// Revision 1.7 2002/01/23 07:52:36 lampret`
`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`	`// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.`
`//`	`//`
`// Revision 1.6 2002/01/18 14:21:43 lampret`	`// Revision 1.6 2002/01/18 14:21:43 lampret`
`// Fixed 'the NPC single-step fix'.`	`// Fixed 'the NPC single-step fix'.`
Line 380...	Line 383...
state <= #1 `OR1200_EXCEPTFSM_IDLE;	state <= #1 `OR1200_EXCEPTFSM_IDLE;
except_type <= #1 `OR1200_EXCEPT_NONE;	except_type <= #1 `OR1200_EXCEPT_NONE;
`extend_flush <= #1 1'b0;`	`extend_flush <= #1 1'b0;`
`epcr <= #1 32'b0;`	`epcr <= #1 32'b0;`
`eear <= #1 32'b0;`	`eear <= #1 32'b0;`
esr <= #1 {1'b1, {`OR1200_SR_WIDTH-3{1'b0}}, 2'b11};	esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
`extend_flush_last <= #1 1'b0;`	`extend_flush_last <= #1 1'b0;`
`end`	`end`
`else begin`	`else begin`
`case (state) // synopsys full_case parallel_case`	`case (state) // synopsys full_case parallel_case`
`OR1200_EXCEPTFSM_IDLE:	`OR1200_EXCEPTFSM_IDLE:

Line 42...

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

//

//

// CVS Revision History

// CVS Revision History

//

//

// $Log: not supported by cvs2svn $

// $Log: not supported by cvs2svn $

// Revision 1.8  2002/01/28 01:16:00  lampret

// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.

//

// Revision 1.7  2002/01/23 07:52:36  lampret

// Revision 1.7  2002/01/23 07:52:36  lampret

// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.

// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.

//

//

// Revision 1.6  2002/01/18 14:21:43  lampret

// Revision 1.6  2002/01/18 14:21:43  lampret

// Fixed 'the NPC single-step fix'.

// Fixed 'the NPC single-step fix'.

Line 380...

Line 383...

                state <= #1 `OR1200_EXCEPTFSM_IDLE;

                state <= #1 `OR1200_EXCEPTFSM_IDLE;

                except_type <= #1 `OR1200_EXCEPT_NONE;

                except_type <= #1 `OR1200_EXCEPT_NONE;

                extend_flush <= #1 1'b0;

                extend_flush <= #1 1'b0;

                epcr <= #1 32'b0;

                epcr <= #1 32'b0;

                eear <= #1 32'b0;

                eear <= #1 32'b0;

                esr <= #1 {1'b1, {`OR1200_SR_WIDTH-3{1'b0}}, 2'b11};

                esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};

                extend_flush_last <= #1 1'b0;

                extend_flush_last <= #1 1'b0;

end

end

        else begin

        else begin

                case (state)    // synopsys full_case parallel_case

                case (state)    // synopsys full_case parallel_case

                        `OR1200_EXCEPTFSM_IDLE:

                        `OR1200_EXCEPTFSM_IDLE:

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[/] [or1k/] [tags/] [rel_20/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Diff between revs 617 and 660