Line 42... |
Line 42... |
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.7 2002/09/03 22:28:21 lampret
|
|
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
|
|
//
|
// Revision 1.6 2002/03/29 16:40:10 lampret
|
// Revision 1.6 2002/03/29 16:40:10 lampret
|
// Added a directive to ignore signed division variables that are only used in simulation.
|
// Added a directive to ignore signed division variables that are only used in simulation.
|
//
|
//
|
// Revision 1.5 2002/03/29 16:33:59 lampret
|
// Revision 1.5 2002/03/29 16:33:59 lampret
|
// Added again just recently removed full_case directive
|
// Added again just recently removed full_case directive
|
Line 91... |
Line 94... |
`include "or1200_defines.v"
|
`include "or1200_defines.v"
|
|
|
module or1200_alu(
|
module or1200_alu(
|
a, b, mult_mac_result, macrc_op,
|
a, b, mult_mac_result, macrc_op,
|
alu_op, shrot_op, comp_op,
|
alu_op, shrot_op, comp_op,
|
result, flagforw, flag_we
|
result, flagforw, flag_we,
|
|
cyforw, cy_we, carry
|
);
|
);
|
|
|
parameter width = `OR1200_OPERAND_WIDTH;
|
parameter width = `OR1200_OPERAND_WIDTH;
|
|
|
//
|
//
|
Line 109... |
Line 113... |
input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
|
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
|
output [width-1:0] result;
|
output [width-1:0] result;
|
output flagforw;
|
output flagforw;
|
output flag_we;
|
output flag_we;
|
|
output cyforw;
|
|
output cy_we;
|
|
input carry;
|
|
|
//
|
//
|
// Internal wires and regs
|
// Internal wires and regs
|
//
|
//
|
reg [width-1:0] result;
|
reg [width-1:0] result;
|
reg [width-1:0] shifted_rotated;
|
reg [width-1:0] shifted_rotated;
|
reg flagforw;
|
reg flagforw;
|
reg flagcomp;
|
reg flagcomp;
|
reg flag_we;
|
reg flag_we;
|
|
reg cy_we;
|
// synopsys translate_off
|
// synopsys translate_off
|
`ifdef OR1200_SIM_ALU_DIV
|
`ifdef OR1200_SIM_ALU_DIV
|
integer d1;
|
integer d1;
|
integer d2;
|
integer d2;
|
`endif
|
`endif
|
Line 131... |
Line 139... |
`ifdef OR1200_IMPL_ALU_COMP1
|
`ifdef OR1200_IMPL_ALU_COMP1
|
wire a_eq_b;
|
wire a_eq_b;
|
wire a_lt_b;
|
wire a_lt_b;
|
`endif
|
`endif
|
wire [width-1:0] result_sum;
|
wire [width-1:0] result_sum;
|
|
`ifdef OR1200_IMPL_ADDC
|
|
wire [width-1:0] result_csum;
|
|
`endif
|
wire [width-1:0] result_and;
|
wire [width-1:0] result_and;
|
|
wire cyforw;
|
|
|
//
|
//
|
// Combinatorial logic
|
// Combinatorial logic
|
//
|
//
|
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
|
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
|
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
|
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
|
`ifdef OR1200_IMPL_ALU_COMP1
|
`ifdef OR1200_IMPL_ALU_COMP1
|
assign a_eq_b = (comp_a == comp_b);
|
assign a_eq_b = (comp_a == comp_b);
|
assign a_lt_b = (comp_a < comp_b);
|
assign a_lt_b = (comp_a < comp_b);
|
`endif
|
`endif
|
assign result_sum = a + b;
|
assign {cyforw, result_sum} = a + b;
|
|
`ifdef OR1200_IMPL_ADDC
|
|
assign {cyforw, result_csum} = a + b + carry;
|
|
`endif
|
assign result_and = a & b;
|
assign result_and = a & b;
|
|
|
//
|
//
|
// Simulation check for bad ALU behavior
|
// Simulation check for bad ALU behavior
|
//
|
//
|
Line 172... |
Line 187... |
result = shifted_rotated;
|
result = shifted_rotated;
|
end
|
end
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
result = result_sum;
|
result = result_sum;
|
end
|
end
|
|
`ifdef OR1200_IMPL_ADDC
|
|
`OR1200_ALUOP_ADDC : begin
|
|
result = result_csum;
|
|
end
|
|
`endif
|
`OR1200_ALUOP_SUB : begin
|
`OR1200_ALUOP_SUB : begin
|
result = a - b;
|
result = a - b;
|
end
|
end
|
`OR1200_ALUOP_XOR : begin
|
`OR1200_ALUOP_XOR : begin
|
result = a ^ b;
|
result = a ^ b;
|
Line 236... |
Line 256... |
//
|
//
|
// Generate flag and flag write enable
|
// Generate flag and flag write enable
|
//
|
//
|
always @(alu_op or result_sum or result_and or flagcomp) begin
|
always @(alu_op or result_sum or result_and or flagcomp) begin
|
casex (alu_op) // synopsys parallel_case
|
casex (alu_op) // synopsys parallel_case
|
|
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
|
`OR1200_ALUOP_ADD : begin
|
`OR1200_ALUOP_ADD : begin
|
flagforw = (result_sum == 32'h0000_0000);
|
flagforw = (result_sum == 32'h0000_0000);
|
flag_we = 1'b0;
|
flag_we = 1'b1;
|
|
end
|
|
`ifdef OR1200_IMPL_ADDC
|
|
`OR1200_ALUOP_ADDC : begin
|
|
flagforw = (result_csum == 32'h0000_0000);
|
|
flag_we = 1'b1;
|
end
|
end
|
|
`endif
|
`OR1200_ALUOP_AND: begin
|
`OR1200_ALUOP_AND: begin
|
flagforw = (result_and == 32'h0000_0000);
|
flagforw = (result_and == 32'h0000_0000);
|
flag_we = 1'b0;
|
flag_we = 1'b1;
|
end
|
end
|
|
`endif
|
`OR1200_ALUOP_COMP: begin
|
`OR1200_ALUOP_COMP: begin
|
flagforw = flagcomp;
|
flagforw = flagcomp;
|
flag_we = 1'b1;
|
flag_we = 1'b1;
|
end
|
end
|
default: begin
|
default: begin
|
Line 256... |
Line 284... |
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
//
|
//
|
|
// Generate SR[CY] write enable
|
|
//
|
|
always @(alu_op) begin
|
|
casex (alu_op) // synopsys parallel_case
|
|
`ifdef OR1200_IMPL_ADDC
|
|
`OR1200_ALUOP_ADDC : begin
|
|
cy_we = 1'b1;
|
|
end
|
|
`endif
|
|
default: begin
|
|
cy_we = 1'b0;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
//
|
// Shifts and rotation
|
// Shifts and rotation
|
//
|
//
|
always @(shrot_op or a or b) begin
|
always @(shrot_op or a or b) begin
|
case (shrot_op) // synopsys parallel_case
|
case (shrot_op) // synopsys parallel_case
|
`OR1200_SHROTOP_SLL :
|
`OR1200_SHROTOP_SLL :
|