OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_cfgr.v] - Diff between revs 504 and 562

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 504 Rev 562
Line 42... Line 42...
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//
//
// CVS Revision History
// CVS Revision History
//
//
// $Log: not supported by cvs2svn $
// $Log: not supported by cvs2svn $
 
// Revision 1.1  2002/01/03 08:16:15  lampret
 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
 
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
// MP3 version.
Line 91... Line 94...
//
//
always @(spr_addr)
always @(spr_addr)
`ifdef OR1200_SYS_FULL_DECODE
`ifdef OR1200_SYS_FULL_DECODE
        if (!spr_addr[31:4])
        if (!spr_addr[31:4])
`endif
`endif
                case(spr_addr[3:0])
                case(spr_addr[3:0])              // synopsys parallel_case
                        `OR1200_SPRGRP_SYS_VR: begin
                        `OR1200_SPRGRP_SYS_VR: begin
                                spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
                                spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
                                spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
                                spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
                                spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG;
                                spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG;
                                spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER;
                                spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER;
Line 176... Line 179...
                                spr_dat_o[`OR1200_DCFGR_WPCI_BITS] = `OR1200_DCFGR_WPCI;
                                spr_dat_o[`OR1200_DCFGR_WPCI_BITS] = `OR1200_DCFGR_WPCI;
                                spr_dat_o[`OR1200_DCFGR_RES1_BITS] = `OR1200_DCFGR_RES1;
                                spr_dat_o[`OR1200_DCFGR_RES1_BITS] = `OR1200_DCFGR_RES1;
                        end
                        end
                        default: spr_dat_o = 32'h0000_0000;
                        default: spr_dat_o = 32'h0000_0000;
                endcase
                endcase
`ifdef SYS_FULL_DECODE
`ifdef OR1200_SYS_FULL_DECODE
        else
        else
                spr_dat_o = 32'h0000_0000;
                spr_dat_o = 32'h0000_0000;
`endif
`endif
 
 
`else
`else

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.